Abstract: Circuitry for measurement of electrochemical cells Circuitry for processing an analyte signal obtained from an electrochemical cell.

Abstract: This application relates to methods and apparatus for sensing current in a monitored current path, where the monitored current path is bidirectional such that current can flow in either direction along the monitored current path. A current sensor has first and second sense resistors (401a, 401b) configured to each pass a current corresponding to the current in the monitored current path. The first and second sense resistors are configured to have a matching arrangement, such that current flow through the first sense resistor when current is flowing in one direction in the monitored current path matches current flow through the second sense resistor when current is flowing in the opposite direction in the monitored current path.

Abstract: The present application relates to current sensing circuitry (100) that comprises a differential amplifier (110) comprising first and second inputs configured to sense a current across a sense resistance, and an output configured to output a current sense signal. The circuitry (100) further comprises a first current source, a second current source and a switch network operable in: a first phase in which the first current source is connected to the first input and disconnected from the output, and the second current source is connected to the output and disconnected from the first input; and a second phase in which the first current source is connected to the output and disconnected from the first input, and the second current source is connected to the first input and disconnected from the output.

Abstract: An auxiliary buffering device comprises upper and lower frames assembled with a bicycle saddle. A first elastic unit is disposed between first ends of the upper and lower frames and is compressible and restorable in a vertical direction. A second elastic unit is disposed between second ends of the upper and lower frames, is compressible and restorable in a horizontal direction, and includes first and second transverse springs. Each of the upper and lower frames includes first and second lateral rods. Two ends of the first transverse spring extend from an end of the first lateral rod of the upper frame and an end of the first lateral rod of the lower frame, respectively. Two ends of the second transverse spring extend from an end of the second lateral rod of the upper frame and an end of the second lateral rod of the lower frame, respectively.

Abstract: The present application relates to current sensing circuitry (100) that comprises a differential amplifier (110) comprising first and second inputs configured to sense a current across a sense resistance, and an output configured to output a current sense signal. The circuitry (100) further comprises a first current source, a second current source and a switch network operable in: a first phase in which the first current source is connected to the first input and disconnected from the output, and the second current source is connected to the output and disconnected from the first input; and a second phase in which the first current source is connected to the output and disconnected from the first input, and the second current source is connected to the first input and disconnected from the output.

Abstract: This application relates to methods and apparatus for sensing current in a monitored current path, where the monitored current path is bidirectional such that current can flow in either direction along the monitored current path. A current sensor has first and second sense resistors (401a, 401b) configured to each pass a current corresponding to the current in the monitored current path. The first and second sense resistors are configured to have a matching arrangement, such that current flow through the first sense resistor when current is flowing in one direction in the monitored current path matches current flow through the second sense resistor when current is flowing in the opposite direction in the monitored current path.

Abstract: The present application relates to current sensing circuitry (100) that comprises a differential amplifier (110) comprising first and second inputs configured to sense a current across a sense resistance, and an output configured to output a current sense signal. The circuitry (100) further comprises a first current source, a second current source and a switch network operable in: a first phase in which the first current source is connected to the first input and disconnected from the output, and the second current source is connected to the output and disconnected from the first input; and a second phase in which the first current source is connected to the output and disconnected from the first input, and the second current source is connected to the first input and disconnected from the output.

Abstract: The present application relates to current sensing circuitry (100) that comprises a differential amplifier (110) comprising first and second inputs configured to sense a current across a sense resistance, and an output configured to output a current sense signal. The circuitry (100) further comprises a first current source, a second current source and a switch network operable in: a first phase in which the first current source is connected to the first input and disconnected from the output, and the second current source is connected to the output and disconnected from the first input; and a second phase in which the first current source is connected to the output and disconnected from the first input, and the second current source is connected to the first input and disconnected from the output.

Abstract: A system for performing data-parallel operations and task-parallel operations. A first switch fabric node (SFN) includes first and second lane processing engines (LPEs). The first LPE includes a first set of lane processing units (LPUs) configured to perform data-parallel operations, where each LPU performs a set of operations, and each LPU uses a different set of data for the set of operations, and each LPU within the first set of LPUs uses a different set of data for the set of operations. The second LPE includes a second set of LPUs configured to perform task-parallel operations, where each LPU performs a different set of operations. A processing control engine (PCE) is configured to distribute instructions and data to the first LPE and the second LPE. Advantageously, data parallel operations and task parallel operations are able to be performed on the same processor simultaneously.

Abstract: The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into first and second vector registers, respectively. Each data element comprises N bits. Next, an arithmetic instruction is fetched from memory. The arithmetic instruction is decoded. Then, the first vector register and the second vector register are read from the register file. The present invention executes the arithmetic instruction on corresponding data elements in the first and second vector registers. The resulting element of the execution is then written into the accumulator. Then, the resulting element is transformed into an N-bit width element and written into a third register for further operation or storage in memory. The transformation of the resulting element can include, for example, rounding, clamping, and/or shifting the element.

Abstract: The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into first and second vector registers, respectively. Each data element comprises N bits. Next, an arithmetic instruction is fetched from memory. The arithmetic instruction is decoded. Then, the first vector register and the second vector register are read from the register file. The present invention executes the arithmetic instruction on corresponding data elements in the first and second vector registers. The resulting element of the execution is then written into the accumulator. Then, the resulting element is transformed into an N-bit width element and written into a third register for further operation or storage in memory. The transformation of the resulting element can include, for example, rounding, clamping, and/or shifting the element.

Abstract: The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into first and second vector registers, respectively. Each data element comprises N bits. Next, an arithmetic instruction is fetched from memory. The arithmetic instruction is decoded. Then, the first vector register and the second vector register are read from the register file. The present invention executes the arithmetic instruction on corresponding data elements in the first and second vector registers. The resulting element of the execution is then written into the accumulator. Then, the resulting element is transformed into an N-bit width element and written into a third register for further operation or storage in memory. The transformation of the resulting element can include, for example, rounding, clamping, and/or shifting the element.

Abstract: The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a first register and another vector is loaded from the memory unit into a second register. The first vector contains a first byte of an aligned vector to be generated. Then, a starting byte specifying the first byte of an aligned vector is determined. Next, a vector is extracted from the first register and the second register beginning from the first bit in the first byte of the first register continuing through the bits in the second register. Finally, the extracted vector is replicated into a third register such that the third register contains a plurality of elements aligned for SIMD processing. In the ordering of vector elements for SIMD processing, a first vector is loaded from a memory unit into a first register and a second vector is loaded from the memory unit into a second register.

Abstract: The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a first register and another vector is loaded from the memory unit into a second register. The first vector contains a first byte of an aligned vector to be generated. Then, a starting byte specifying the first byte of an aligned vector is determined. Next, a vector is extracted from the first register and the second register beginning from the first bit in the first byte of the first register continuing through the bits in the second register. Finally, the extracted vector is replicated into a third register such that the third register contains a plurality of elements aligned for SIMD processing. In the ordering of vector elements for SIMD processing, a first vector is loaded from a memory unit into a first register and a second vector is loaded from the memory unit into a second register.

Abstract: The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into a first vector register and a second vector register, respectively. Each data element comprises N bits. Next, an arithmetic instruction is fetched from memory. The arithmetic instruction is decoded. Then, a first vector register and a second vector register are read from the register file. The present invention then executes the arithmetic instruction on corresponding data elements in the first and second vector registers. The result of the execution is then written into the accumulator. Then, each element in the accumulator is transformed into an N-bit width element and stored into the memory.

Abstract: Previously conducted conversations in real-time collaboration messages are persistently stored, either by client or a server, and then are associated with conversational items presented to a user (e.g. contact names, topics, etc.). An icon is provided near each listed item, which when selected, displays to the user summaries or titles of all transcripts to which the selected item pertains or relates. The user may select one or more summaries or titles for which the conversation is to be resumed, causing the system to retrieve the stored transcript and resume appending new conversational entries to it, so that the user recovers conversational context effortlessly and accurately. Enhanced versions of the invention include sharing of transcripts so that all participants receive the context of the conversation, and server-side or client-side implementations.

Abstract: The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into first and second vector registers, respectively. Each data element comprises N bits. Next, an arithmetic instruction is fetched from memory. The arithmetic instruction is decoded. Then, the first vector register and the second vector register are read from the register file. The present invention executes the arithmetic instruction on corresponding data elements in the first and second vector registers. The resulting element of the execution is then written into the accumulator. Then, the resulting element is transformed into an N-bit width element and written into a third register for further operation or storage in memory. The transformation of the resulting element can include, for example, rounding, clamping, and/or shifting the element.

Abstract: An external hanging touch screen including a touch panel and a controller, wherein the touch panel is fabricated from a transparent material. The present invention is characterized in that a rectangular frame is constructed around an edging of the touch panel, and an inner side edging of the frame is slightly smaller than the touch panel, while an outer edging of the frame corresponds to an outer edging of a screen front cover of the monitor. Accordingly, aforementioned configuration utilizes the frame to hang on the screen front cover of the computer monitor, thereby producing an effect of protecting the monitor, moreover, the touch screen can be assembled and dismantled at anytime, thus furnishing flexibility in usage to a user, and achieving effectiveness of economical benefit.

Abstract: An alarm system and method by which a user can be alerted to a detected condition regarding their vehicle, can view what is happening in and around the vehicle, and can remotely turn off or reset the alarm if it is determined that an alarm is false. This is provided using one or more cameras and a cellular telephone to which the pictures can be sent.

Abstract: A method to convert surplus nitroarene explosives into trinitrophloroglucinol and triaminotrinitrobenzene (TATB) is described. Picric acid is directly aminated to diaminopicric acid, which is converted to trinitrophloroglucinol and triaminotrinitrobenzene.