Abstract: The invention provides a technique of monitoring the void formation in a damascene interconnection process. According to the invention, a test structure is provided that includes at least two damascene structures that have at least one different cross-sectional geometric parameter. To monitor the void formation, the test structure is cut to expose a cross-sectional view to the damascene structures. The cross-sectional view is then inspected and the void formation is investigated in each of the damascene structures. The invention is particularly applicable to multi-level copper-based dual-damascene interconnection processes to monitor the voiding at the interface between barrier layers and bottom metal trenches. The invention allows monitoring of the void formation by locating only one structure on the chip and performing only one cut.

Abstract: A copper line that is formed in a patterned dielectric layer has a copper/silicon film formed on a surface thereof to substantially suppress an electromigration path through this surface. In an in situ process, the exposed copper surface is first cleaned by a reactive plasma ambient including nitrogen and ammonia and after a certain clean period, a gaseous compound comprising silicon, for example silane, is added to the reactive plasma ambient to form the copper/silicon film. Additionally, a capping layer may be deposited, wherein due to the copper/silicon film, any deposition technique or even spin-coating may be used.

Abstract: For determining the quality of interconnections in integrated circuits, especially in damascene applications, a method of monitoring voids is disclosed, wherein a barrier metal layer is directly deposited on a planarized metal to provide a large-area surface that is not required to be destroyed for further analysis of the interface between the metal and the barrier metal layer. The analysis may be carried out by employing an electron microscope operated in a back-scatter mode.

Abstract: A copper line that is formed in a patterned dielectric layer has a copper/silicon film formed on a surface thereof to substantially suppress an electromigration path through this surface. In an in situ process, the exposed copper surface is first cleaned by a reactive plasma ambient including nitrogen and ammonia and after a certain clean period, a gaseous compound comprising silicon, for example silane, is added to the reactive plasma ambient to form the copper/silicon film. Additionally, a capping layer may be deposited, wherein due to the copper/silicon film, any deposition technique or even spin-coating may be used.

Abstract: In an in situ damascene metallization process employing a barrier layer between the metal and the dielectric, the generation of voids, especially at the bottom of vias, can be significantly reduced or even completely avoided by maintaining the surface temperature below a critical temperature during deposition of the barrier material.

Abstract: The invention provides a technique of monitoring the void formation in a damascene interconnection process. According to the invention, a test structure is provided that includes at least two damascene structures that have at least one different cross-sectional geometric parameter. To monitor the void formation, the test structure is cut to expose a cross-sectional view to the damascene structures. The cross-sectional view is then inspected and the void formation is investigated in each of the damascene structures. The invention is particularly applicable to multi-level copper-based dual-damascene interconnection processes to monitor the voiding at the interface between barrier layers and bottom metal trenches. The invention allows monitoring of the void formation by locating only one structure on the chip and performing only one cut.

Abstract: In an in situ damascene metallization process employing a barrier layer between the metal and the dielectric, the generation of voids, especially at the bottom of vias, can be significantly reduced or even completely avoided by maintaining the surface temperature below a critical temperature during deposition of the barrier material.

Abstract: For determining the quality of interconnections in integrated circuits, especially in damascene applications, a method of monitoring voids is disclosed, wherein a barrier metal layer is directly deposited on a planarized metal to provide a large-area surface that is not required to be destroyed for further analysis of the interface between the metal and the barrier metal layer. The analysis may be carried out by employing an electron microscope operated in a back-scatter mode.