Abstract: The present disclosure provides a buffer amplifier arrangement that seeks to find a solution to varying load configurations, output modes, modulator modes etc on an output of the buffer and the corresponding varying currents or voltages that appear at transistor devices throughout the circuit. To address this issue a current source that supplies an output of the buffer is divided into a fixed current source which supplies the current for the transistors of the buffer, and a variable current source that provides current for the variable load. The variable current source is a programmable current source that can be varied based on the associated modulator mode bus.

Abstract: A data platform connecting the functions of digital measurement, reporting, and verification (dMRV) of emissions mitigation activities and securitization of emissions credits from the verified emissions mitigation activity data.

Abstract: A combination amplifier can include a “main amplifier circuit” for signal amplification, and a matching “compensation amplifier circuit” to monitor distortion in the main amplifier output signal. The compensation amplifier circuit provides a compensation signal to the main amplifier circuit to compensate for and servo out distortion therein. The compensation amplifier circuit includes a passive input network and an amplifier. The passive input network can connect to both the input and output nodes of the main amplifier circuit such that the input and output signals cancel within the passive input network, leaving only the low level distortion component introduced in the main amplifier. Thus, the compensation amplifier is then only operating on the low-level distortion introduced in the main amplifier to generate the compensation signal. Because the compensation amplifier is then only operating on the very low distortion signal, any distortion it introduces into the compensation signal is negligible.

Abstract: Systems, devices, and methods related to low-noise, high-accuracy single-ended continuous-time sigma-delta (CTSD) analog-to-digital converter (ADC) are provided. An example single-ended CTSD ADC includes a pair of input nodes to receive a single-ended input signal and input circuitry. The input circuitry includes a pair of switches, each coupled to one of the pair of input nodes; and an amplifier to provide a common mode signal at a pair of first nodes, each before one of the pair of switches. The single-ended CTSD ADC further includes digital-to-analog converter (DAC) circuitry; and integrator circuitry coupled to the input circuitry and the DAC circuitry via a pair of second nodes.

Abstract: A combination amplifier can include a “main amplifier circuit” for signal amplification, and a matching “compensation amplifier circuit” to monitor distortion in the main amplifier output signal. The compensation amplifier circuit provides a compensation signal to the main amplifier circuit to compensate for and servo out distortion therein. The compensation amplifier circuit includes a passive input network and an amplifier. The passive input network can connect to both the input and output nodes of the main amplifier circuit such that the input and output signals cancel within the passive input network, leaving only the low level distortion component introduced in the main amplifier. Thus, the compensation amplifier is then only operating on the low-level distortion introduced in the main amplifier to generate the compensation signal. Because the compensation amplifier is then only operating on the very low distortion signal, any distortion it introduces into the compensation signal is negligible.

Abstract: A stage, suitable for use in an analog to digital converter or a digital to analog converter, can have a plurality of slices that can be operated together to form a composite output. The stage can have reduced thermal noise, while each slice on its own has sufficiently small capacitance to respond quickly to changes in digital codes applied to the slice. This feature allows a fast conversion to be achieved without loss of noise performance.

Abstract: A pre-charge circuit is provided for pre-charging the input node of a capacitive component to which the multiplexer output is fed to a charge level that is close to or approximates the signal output level of the multiplexer when its output is next switched. In order to reduce the level shifting burden on the amplifier in the pre-charge circuit, each pre-charge circuit input channel has a respective capacitor that is able to be switched in and out of series with the respective multiplexer channels, such that the respective capacitors track the signal levels on the multiplexer channels. The provision of the corresponding capacitors for each MUX channel reduces the input current to the pre-charge amplifier, and allows for the level shifting burden to be taken by the capacitors, leading to more stable and lower power operation.

Abstract: The present disclosure provides alternative solutions to the problem of providing a stable voltage reference to high speed ADCs that possess high sampling rates. In one example the high speed amplifier is replaced by a smaller, slower, lower power amplifier in combination with a relatively large capacitor connected to the same node as the amplifier output and the ADC reference input. The capacitor is charged substantially to the external reference voltage and hence keeps the reference input of the ADC almost at the external reference voltage between conversions, such that when conversion is about to occur and the external reference is switched in then very little charge is required from the external reference, and hence the reference signal quickly settles.

Abstract: A switched-capacitor integrator is described having the contribution to offset from the charge injection mismatch of switches connected to the summing nodes mitigated by using a switching scheme that conveys basically all the charge injection to the output, thus preventing net offset from being integrated.

Abstract: Noise sources in an ADC circuit can include kT/C noise of a sampling capacitor, noise coupling on to sampling capacitors from digital circuits, and amplifier noise. Also, charge injection from mismatch in sample switches can cause offsets. These various noise sources can be largely canceled or reduced using described techniques. As a result, the size of the sampling capacitors can be greatly reduced, while still achieving significantly improved noise performance and power efficiency for the overall converter.

Abstract: An electronic circuit comprises multiple analog-to-digital converter (ADC) circuits and control logic circuitry. The control logic circuitry advances the multiple ADC circuits through multiple time-interleaved conversions that include time-interleaved acquisition phases, conversion phases, and tracking phases. An acquisition phase of a first ADC circuit samples the analog signal, a conversion phase of the first ADC circuit converts the sampled analog signal to a digital value, and the control logic circuitry is configured to update the first ADC circuit with most recent A/D conversion information by a different ADC circuit during a tracking phase of the first ADC circuit before the acquisition phase of the first ADC circuit.

Abstract: A stage, suitable for use in an analog to digital converter or a digital to analog converter where the stage comprises a plurality of slices that can be operated together to form a composite output, can have reduced thermal noise, whilst each slice on its own has sufficiently small capacitance to respond quickly to changes in digital codes applied to the slice. This allows a fast conversion to be achieved without loss of noise performance.

Abstract: Input stages for an analog to digital converter wherein charge for charging parasitic capacitances in the input stage, and particularly in the input switch is sourced from a node which means that it does not have to pass through the input RC filter. This has the effect that the input RC filter can be of lower bandwidth, and/or have a larger resistor value, with the consequent result that there is lower power dissipation in the ADC drive circuitry. In one example this effect is realized by providing a separate input into which charge to charge the parasitic capacitances can be fed from external circuitry. In another example an operational amplifier having high (ideally infinite) input impedance can be used to feed charge to the input switch from the input to the RC filter, or from the node between the resistor and capacitor of the filter, again without unsettling the filter.

Abstract: Techniques for supplying a bias current to a load are provided. In certain examples, a circuit can include a level-shift capacitance, a current source, and a load configured to receive a bias current in a first state of the circuit. The current source and the level-shift capacitance can be coupled in series between the load and a supply voltage in the first state. In some examples, during a second state of the circuit, the level-shift capacitance can receive charge, and can be isolated from one of the load or the current source.

Abstract: A stage, suitable for use in an analog to digital converter or a digital to analog converter, can have a plurality of slices that can be operated together to form a composite output. The stage can have reduced thermal noise, while each slice on its own has sufficiently small capacitance to respond quickly to changes in digital codes applied to the slice. This feature allows a fast conversion to be achieved without loss of noise performance.

Abstract: A stage, suitable for use in and analog to digital converter or a digital to analog converter, comprises a plurality of slices. The slices can be operated together to form a composite output having reduced thermal noise, while each slice on its own has sufficiently small capacitance to respond quickly to changes in digital codes applied to the slice. This allows a fast conversion to be achieved without loss of noise performance. The slices can be sub-divided to reduce scaling mismatch between the most significant bit and the least significant bit. A shuffling scheme is implemented that allows shuffling to occur between the sub-sections of the slices without needing to implement a massively complex shuffler.

Abstract: A dither is an uncorrelated signal, usually pseudo-random noise injected into the input of an ADC such that a given input value of the wanted signal becomes spread over a plurality of codes. This reduces the effect of DNL and also smooths the integral non-linearity (INL) response of the ADC. The advantages of introducing dither could be obtained without having to perturb the signal input to the ADC. This avoids the introduction of additional components in the ADC. The dither can be applied to the components used to form a residue of the ADC stage within a pipelined converter. For example, a dither can be applied solely to a DAC part or different dithers can be applied to a ADC and DAC parts respectively. This allows greater flexibility of linearization of the ADC response and the formation of an analog residue by the DAC.

Abstract: Techniques for supplying a bias current to a load are provided. In certain examples, a circuit can include a level-shift capacitance, a current source, and a load configured to receive a bias current in a first state of the circuit. The current source and the level-shift capacitance can be coupled in series between the load and a supply voltage in the first state. In some examples, during a second state of the circuit, the level-shift capacitance can receive charge, and can be isolated from one of the load or the current source.

Abstract: A stage, suitable for use in and analog to digital converter or a digital to analog converter, comprises a plurality of slices. The slices can be operated together to form a composite output having reduced thermal noise, while each slice on its own has sufficiently small capacitance to respond quickly to changes in digital codes applied to the slice. This allows a fast conversion to be achieved without loss of noise performance. The slices can be sub-divided to reduce scaling mismatch between the most significant bit and the least significant bit. A shuffling scheme is implemented that allows shuffling to occur between the sub-sections of the slices without needing to implement a massively complex shuffler.

Abstract: A stage, suitable for use in an analog to digital converter or a digital to analog converter, can have a plurality of slices that can be operated together to form a composite output. The stage can have reduced thermal noise, while each slice on its own has sufficiently small capacitance to respond quickly to changes in digital codes applied to the slice. This feature allows a fast conversion to be achieved without loss of noise performance.