Patents by Inventor Peter I. A. Barri
Peter I. A. Barri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7643511Abstract: Packet switching node in a communication system includes apparatus for receiving incoming information packets or frames which contain header portions with formatting control blocks. Information in the frame's header contains frame alteration commands for modifying the information in the frame. The modifications include adding new information, deleting information, and overlaying information. Decoders and control devices in an alteration engine interpret the commands and apply the modifications to the frame data. Common and standard data patterns are stored for insertion or overlaying to conserve data packet space.Type: GrantFiled: December 3, 2008Date of Patent: January 5, 2010Assignee: International Business Machines CorporationInventors: Peter I. A. Barri, Claude Basso, Jean L. Calvignac, Brahmanand K. Gorti, Joseph F. Logan, Natarajan Valdhyanathan, Johan G. A. Verkinderen
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Publication number: 20090080461Abstract: Packet switching node in a communication system includes apparatus for receiving incoming information packets or frames which contain header portions with formatting control blocks. Information in the frame's header contains frame alteration commands for modifying the information in the frame. The modifications include adding new information, deleting information, and overlaying information. Decoders and control devices in an alteration engine interpret the commands and apply the modifications to the frame data. Common and standard data patterns are stored for insertion or overlaying to conserve data packet space.Type: ApplicationFiled: December 3, 2008Publication date: March 26, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: PETER I. A. BARRI, CLAUDE BASSO, JEAN L. CALVIGNAC, BRAHMANAND K. GORTI, JOSEPH F. LOGAN, NATARAJAN VALDHYANATHAN, JOHAN G. A. VERKINDEREN
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Patent number: 7474672Abstract: Packet switching node in a communication system includes apparatus for receiving incoming information packets or frames which contain header portions with formatting control blocks. Information in the frame's header contains frame alteration commands for modifying the information in the frame. The modifications include adding new information, deleting information, and overlaying information. Decoders and control devices in an alteration engine interpret the commands and apply the modifications to the frame data. Common and standard data patterns are stored for insertion or overlaying to conserve data packet space.Type: GrantFiled: February 11, 2003Date of Patent: January 6, 2009Assignee: International Business Machines CorporationInventors: Peter I. A. Barri, Claude Basso, Jean L. Calvignac, Brahmanand K. Gorti, Joseph F. Logan, Natarajan Vaidhyanathan, Johan G. A. Verkinderen
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Publication number: 20040156368Abstract: Packet switching node in a communication system includes apparatus for receiving incoming information packets or frames which contain header portions with formatting control blocks. Information in the frame's header contains frame alteration commands for modifying the information in the frame. The modifications include adding new information, deleting information, and overlaying information. Decoders and control devices in an alteration engine interpret the commands and apply the modifications to the frame data. Common and standard data patterns are stored for insertion or overlaying to conserve data packet space.Type: ApplicationFiled: February 11, 2003Publication date: August 12, 2004Applicants: International Business Machines Corporation, AlcatelInventors: Peter I. A. Barri, Claude Basso, Jean L. Calvignac, Brahmanand K. Gorti, Joseph F. Logan, Natarajan Vaidhyanathan, Johan G. A. Verkinderen
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Patent number: 6757795Abstract: A Network Processor (NP) includes a controller that allows maximum utilization of the memory. The controller includes a memory arbiter that monitors memory access requests from requesters in the NP and awards high priority requesters all the memory bandwidth requested per access to the memory. If the memory bandwidth requested by the high priority requester is less than the full memory bandwidth, the difference between the requested bandwidth and full memory bandwidth is assigned to lower priority requesters. By so doing every memory access utilizes the full memory bandwidth.Type: GrantFiled: February 5, 2002Date of Patent: June 29, 2004Assignees: International Business Machines Corporation, AlcatelInventors: Peter I. A. Barri, Jean L. Calvignac, Marco C. Heddes, Joseph F. Logan, Alex M. M. Niemegeers, Fabrice J. Verplanken, Miroslav Vrana
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Publication number: 20020141256Abstract: A Network Processor (NP) includes a controller that allows maximum utilization of the memory. The controller includes a memory arbiter that monitors memory access requests from requesters in the NP and awards high priority requesters all the memory bandwidth requested per access to the memory. If the memory bandwidth requested by the high priority requester is less than the full memory bandwidth, the difference between the requested bandwidth and full memory bandwidth is assigned to lower priority requesters. By so doing every memory access utilizes the full memory bandwidth.Type: ApplicationFiled: February 5, 2002Publication date: October 3, 2002Applicant: International Business Machines CorporationInventors: Peter I.A. Barri, Jean L. Calvignac, Marco C. Heddes, Joseph F. Logan, Alex M. M. Niemegeers, Fabrice J. Verplanken, Miroslav Vrana
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Patent number: 5271002Abstract: Communication switching element (SE) with a plurality of input receiver circuits (RC01/16), a plurality of output transmitter circuits (TC01/17), and a plurality of control circuits (CMC01/08) each with a data write bus (DB01/08), with a plurality of data buffers (DB0101/1601); DB0108/1608) coupling the input circuits to the data bus, and with a plurality of RAMs (RAM0101/1701; RAM0108/1708) each with an input individually connected to the data write bus and with an output individually connected to a respective one of the output circuits.Type: GrantFiled: August 2, 1990Date of Patent: December 14, 1993Assignee: Alcatel N.V.Inventors: Peter I. A. Barri, Jan L. B. De Groote
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Patent number: 5210742Abstract: Communication system and switching element used therein. To detect and remove partly established paths, a path release explorer packet is periodically transmitted from an outside node on established paths and each time it arrives in a node a check is made whether this node is a dead end for all directions. In the affirmative a path release packet is transmitted to a preceding node to possibly release the path to the dead end node. The switching element used in each node includes a first switching bus (TB, TM) to interconnect input ports (RX1/8) to output ports (TX1/8). One of these output ports (TX9) is connected to a second switching bus (SB) which has access to all input ports.Type: GrantFiled: October 31, 1990Date of Patent: May 11, 1993Assignee: Alcatel N.V.Inventors: Peter I. A. Barri, Luc O. Beyne
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Patent number: 5199027Abstract: Communication switching system wherein for each cell stream to be transmitted through a switching element a virtual path is established from an input link to an output link of this element on the basis of the individual bandwidth used by this cell stream and of the then calculated total bandwidth used on this output link. For each cell stream a maintenance cell containing the individual cell stream bandwidth is transmitted on the corresponding virtual path and by means of these maintenance cells the total bandwidth used on each output link is re-calculated and it is checked if it is equal to the above mentioned calculated total bandwidth. The latter is adjusted if a difference is detected.Type: GrantFiled: November 5, 1990Date of Patent: March 30, 1993Assignee: Alcatel N.V.Inventor: Peter I. A. Barri
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Patent number: 5027351Abstract: An asynchronous time division communication system having at least one station including a buffer and an associated processor for writing data packets into said buffer at a sending clock frequency, and for reading data packets from said buffer at a receiving clock frequency. The processor is further capable of assessing the real packet filling level of the buffer and adjusting the receiving clock frequency in corresponding relationship to the assessed real packet filling level. The processor calculates a mean packet filling level after a measured time has elapsed by using the mean of m successively assessed real packet filling levels of said buffer and using the calculated mean packet filling level for adjusting the receiving clock frequency.Type: GrantFiled: September 18, 1989Date of Patent: June 25, 1991Assignee: Alcatel N.V.Inventors: Martin L. F. De Prycker, Mark L. M. R. Ryckebusch, Peter I. A. Barri
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Patent number: 4916690Abstract: A switching network including one or more switching circuits and a control circuit (CCC), the switching circuit including a time division switching element (SR12-SR78) provided with inputs and outputs for data packets and the switching element being controlled by the control circuit (CCC). This switching element is constituted by a closed loop shift register (SR12-SR78) of which all the stages are controlled by a clock signal (f2) provided by the control circuit (CCC) and form a number of shift register portions (SR12-SR78) which are each (SR12) associated to a parallel input (h12) having access to all stages of this portion. A plurality of inputs (R1/2) of the switching element have access to this parallel input (h12) via a multiplexer (MUX12).Type: GrantFiled: May 6, 1988Date of Patent: April 10, 1990Assignee: Alcatel N.V.Inventor: Peter I. A. Barri