Patents by Inventor Peter IRSIGLER

Peter IRSIGLER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11506599
    Abstract: A fluid sensor includes a substrate having a top main surface region, wherein the top main surface region of the substrate forms a common system plane of the fluid sensor, a thermal radiation emitter on the top main surface region of the substrate, an optical filter structure on the top main surface region of the substrate, a waveguide on the main top surface region of the substrate, and a thermal radiation detector on the top main surface region of the substrate, wherein the thermal radiation detector provides a detector output signal based on a radiation strength of the filtered thermal radiation received from the waveguide.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: November 22, 2022
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Thomas Grille, Cristina Consani, Peter Irsigler, Bernhard Jakoby, Thomas Krotscheck Ostermann, Gerald Puehringer, Christian Ranacher, Andreas Tortschanoff
  • Publication number: 20220285550
    Abstract: A method of manufacturing a semiconductor body includes forming a pattern at a first side of a substrate, forming a semiconductor layer on the first side of the substrate, attaching the substrate and the semiconductor layer to a carrier via a surface of the semiconductor layer, and removing the substrate from a second side opposite to the first side.
    Type: Application
    Filed: May 25, 2022
    Publication date: September 8, 2022
    Inventors: Markus Zundel, Andreas Meiser, Hans-Peter Lang, Thorsten Meyer, Peter Irsigler
  • Patent number: 11286158
    Abstract: A MEMS component includes a semiconductor substrate stack having a first semiconductor substrate and a second semiconductor substrate, wherein the semiconductor substrate stack has a cavity formed within the first and second semiconductor substrates, and wherein at least the first or the second semiconductor substrate has an access opening for gas exchange between the cavity and an environment. A radiation source is arranged at the first semiconductor substrate, and a radiation detector is arranged at the second semiconductor substrate. Two mutually spaced apart reflection elements are arranged in a beam path between the radiation source and the radiation detector, wherein one reflection element is partly transmissive to the emitted radiation from the cavity in the direction of the radiation detector, and wherein an interspace between the two mutually spaced apart reflection elements has a length that is at least ten times the wavelength of the emitted radiation.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: March 29, 2022
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Christian Ranacher, Banafsheh Abasahl, Cristina Consani, Thomas Grille, Peter Irsigler, Andreas Tortschanoff
  • Patent number: 11193885
    Abstract: In accordance with an embodiment, a gas sensor includes a substrate having a cavity for providing an optical interaction path; a thermal emitter configured to emit broadband IR radiation; a wavelength selective structure configured to filter the broadband IR radiation emitted by the thermal emitter; and an IR detector configured to provide a detector output signal based on a strength of the filtered IR radiation having traversed the optical interaction path.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: December 7, 2021
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Andreas Tortschanoff, Cristina Consani, Thomas Grille, Peter Irsigler, Christian Ranacher
  • Patent number: 11158707
    Abstract: A transistor device may include a semiconductor body, a plurality of cell regions each comprising a plurality of transistor cells that are at least partially integrated in the semiconductor body and that each comprise a respective gate electrode, a plurality of routing channels each arranged between two or more of the cell regions, a gate pad arranged above a first surface of the semiconductor body, and a plurality of gate runners each coupled to the gate pad and each arranged in one of the plurality of routing channels. Each of the plurality of gate runners may be associated with one of the plurality of cell regions such that the gate electrodes in each of the plurality of cell regions are connected to an associated gate runner, and each of the plurality of routing channels comprises two or more gate runners that are routed in parallel and spaced apart.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: October 26, 2021
    Assignee: Infineon Technologies AG
    Inventors: Hanno Melzner, Markus Dankerl, Peter Irsigler, Sebastian Schmidt, Hans-Joachim Schulze
  • Patent number: 11081382
    Abstract: A method for processing a substrate assembly with a semiconductor device layer includes: arranging an auxiliary carrier at the substrate assembly such that a connection surface of the auxiliary carrier and a first surface of the substrate assembly directly adjoin each other; fixedly attaching the auxiliary carrier to the substrate assembly by melting a carrier portion of the auxiliary carrier and a substrate portion of the substrate assembly that directly adjoins the carrier portion such that the auxiliary carrier and the substrate assembly locally fuse only in fused portions of the auxiliary carrier and the substrate assembly, wherein the fused portions are laterally separated from each other by at least one unfused portion; and processing the semiconductor device layer of the substrate assembly with the auxiliary carrier fixedly attached to the substrate assembly.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: August 3, 2021
    Assignee: Infineon Technologies AG
    Inventors: Francisco Javier Santos Rodriguez, Peter Irsigler
  • Patent number: 11069626
    Abstract: A molding compound and a semiconductor arrangement with a molding compound are disclosed. The molding compound includes a matrix and a filler including filler particles. The filler particles each include a core with an electrically conducting or a semiconducting material and an electrically insulating cover.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: July 20, 2021
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Oliver Hellmund, Peter Irsigler, Hanno Melzner, Stefan Miethaner, Sebastian Schmidt, Hans-Joachim Schulze
  • Publication number: 20210118992
    Abstract: A transistor device may include a semiconductor body, a plurality of cell regions each comprising a plurality of transistor cells that are at least partially integrated in the semiconductor body and that each comprise a respective gate electrode, a plurality of routing channels each arranged between two or more of the cell regions, a gate pad arranged above a first surface of the semiconductor body, and a plurality of gate runners each coupled to the gate pad and each arranged in one of the plurality of routing channels. Each of the plurality of gate runners may be associated with one of the plurality of cell regions such that the gate electrodes in each of the plurality of cell regions are connected to an associated gate runner, and each of the plurality of routing channels comprises two or more gate runners that are routed in parallel and spaced apart.
    Type: Application
    Filed: September 2, 2020
    Publication date: April 22, 2021
    Inventors: Hanno Melzner, Markus Dankerl, Peter Irsigler, Sebastian Schmidt, Hans-Joachim Schulze
  • Publication number: 20210020626
    Abstract: A half-bridge circuit includes a low-side transistor and a high-side transistor each having a load path and a control terminal, and a high-side drive circuit having a level shifter with a level shifter transistor. The low-side transistor and the level shifter transistor are integrated in a common semiconductor body.
    Type: Application
    Filed: October 7, 2020
    Publication date: January 21, 2021
    Inventors: Armin Willmeroth, Franz Hirler, Peter Irsigler
  • Publication number: 20200402832
    Abstract: A method for processing a substrate assembly with a semiconductor device layer includes: arranging an auxiliary carrier at the substrate assembly such that a connection surface of the auxiliary carrier and a first surface of the substrate assembly directly adjoin each other; fixedly attaching the auxiliary carrier to the substrate assembly by melting a carrier portion of the auxiliary carrier and a substrate portion of the substrate assembly that directly adjoins the carrier portion such that the auxiliary carrier and the substrate assembly locally fuse only in fused portions of the auxiliary carrier and the substrate assembly, wherein the fused portions are laterally separated from each other by at least one unfused portion; and processing the semiconductor device layer of the substrate assembly with the auxiliary carrier fixedly attached to the substrate assembly.
    Type: Application
    Filed: June 17, 2020
    Publication date: December 24, 2020
    Inventors: Francisco Javier Santos Rodriguez, Peter Irsigler
  • Patent number: 10833066
    Abstract: A half-bridge circuit includes a low-side transistor and a high-side transistor each having a load path and a control terminal, and a high-side drive circuit having a level shifter with a level shifter transistor. The low-side transistor and the level shifter transistor are integrated in a common semiconductor body.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: November 10, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Armin Willmeroth, Franz Hirler, Peter Irsigler
  • Publication number: 20200309686
    Abstract: A fluid sensor includes a substrate having a top main surface region, wherein the top main surface region of the substrate forms a common system plane of the fluid sensor, a thermal radiation emitter on the top main surface region of the substrate, an optical filter structure on the top main surface region of the substrate, a waveguide on the main top surface region of the substrate, and a thermal radiation detector on the top main surface region of the substrate, wherein the thermal radiation detector provides a detector output signal based on a radiation strength of the filtered thermal radiation received from the waveguide.
    Type: Application
    Filed: March 25, 2020
    Publication date: October 1, 2020
    Inventors: Thomas Grille, Cristina Consani, Peter Irsigler, Bernhard Jakoby, Thomas Krotscheck Ostermann, Gerald Puehringer, Christian Ranacher, Andreas Tortschanoff
  • Publication number: 20200284721
    Abstract: In accordance with an embodiment, a gas sensor includes a substrate having a cavity for providing an optical interaction path; a thermal emitter configured to emit broadband IR radiation; a wavelength selective structure configured to filter the broadband IR radiation emitted by the thermal emitter; and an IR detector configured to provide a detector output signal based on a strength of the filtered IR radiation having traversed the optical interaction path.
    Type: Application
    Filed: February 27, 2020
    Publication date: September 10, 2020
    Inventors: Andreas Tortschanoff, Cristina Consani, Thomas Grille, Peter Irsigler, Christian Ranacher
  • Patent number: 10707865
    Abstract: Devices and methods are provided where a control terminal resistance of a transistor device is set depending on operating conditions within a specified range of operating conditions.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: July 7, 2020
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Anton Mauder, Martina Seider-Schmidt, Hans-Joachim Schulze, Oliver Hellmund, Sebastian Schmidt, Peter Irsigler
  • Patent number: 10670972
    Abstract: A method for exposing a structure on a substrate includes positioning of an invariable reticle and a programmable reticle in a light path between a light source and a layer on a substrate to be exposed to light and exposing the layer on the substrate by light from the light source passing the invariable reticle and the programmable reticle.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: June 2, 2020
    Assignee: Infineon Technologies AG
    Inventors: Rudolf Zelsacher, Peter Irsigler
  • Patent number: 10665705
    Abstract: A method of processing a semiconductor device, comprising: providing a semiconductor body having dopants of a first conductivity type; forming at least one trench that extends into the semiconductor body along a vertical direction, the trench being laterally confined by two trench sidewalls and vertically confined by a trench bottom; applying a substance onto at least a section of a trench surface formed by one of the trench sidewalls and/or the trench bottom of the at least one trench, such that applying the substance includes preventing that the substance is applied to the other of the trench sidewalls; and diffusing of the applied substance from the section into the semiconductor body, thereby creating, in the semiconductor body, a semiconductor region having dopants of a second conductivity type and being arranged adjacent to the section.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: May 26, 2020
    Assignee: Infineon Technologies AG
    Inventors: Thomas Wuebben, Peter Irsigler, Hans-Joachim Schulze
  • Patent number: 10607839
    Abstract: A method includes kicking out impurity atoms from substitutional sites of a crystal lattice of a semiconductor body by implanting particles via a first surface into the semiconductor body, reducing a thickness of the semiconductor body by removing semiconductor material of the semiconductor body, and annealing the semiconductor body in a first annealing process at a temperature of between 300° C. and 450° C. to diffuse impurity atoms out of the semiconductor body.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: March 31, 2020
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Peter Irsigler, Thomas Wuebben
  • Patent number: 10566426
    Abstract: A body structure and a drift zone are formed in a semiconductor layer, wherein the body structure and the drift zone form a first pn junction. A silicon nitride layer is formed on the semiconductor layer. A silicon oxide layer is formed from at least a vertical section of the silicon nitride layer by oxygen radical oxidation.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: February 18, 2020
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Oliver Hellmund, Peter Irsigler, Jens Peter Konrath, David Laforet, Maik Langner, Markus Neuber, Hans-Joachim Schulze, Ralf Siemieniec, Knut Stahrenberg, Olaf Storbeck
  • Patent number: 10553675
    Abstract: In accordance with an embodiment of an integrated circuit, a cavity is buried in a semiconductor body below a first surface of the semiconductor body. An active area portion of the semiconductor body is arranged between the first surface and the cavity. The integrated circuit further includes a trench isolation structure configured to provide a lateral electric isolation of the active area portion.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: February 4, 2020
    Assignee: Infineon Technologies AG
    Inventors: Sebastian Schmidt, Donald Dibra, Oliver Hellmund, Peter Irsigler, Andreas Meiser, Hans-Joachim Schulze, Martina Seider-Schmidt, Robert Wiesner
  • Patent number: 10461203
    Abstract: A semiconductor device comprises a plurality of quantum structures comprising predominantly germanium. The plurality of quantum structures are formed on a first semiconductor layer structure. The quantum structures of the plurality of quantum structures have a lateral dimension of less than 15 nm and an area density of at least 8×1011 quantum structures per cm2. The plurality of quantum structures are configured to emit light with a light emission maximum at a wavelength of between 2 ?m and 10 ?m or to absorb light with a light absorption maximum at a wavelength of between 2 ?m and 10 ?m.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: October 29, 2019
    Assignee: Infineon Technologie AG
    Inventors: Stefan Clara, Thomas Grille, Ursula Hedenig, Peter Irsigler, Bernhard Jakoby, Ventsislav M. Lavchiev, Thomas Ostermann, Thomas Popp