Patents by Inventor Peter J. Andrews

Peter J. Andrews has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9313329
    Abstract: A method for voice browsing an integrated voice response server is described. The method includes visually displaying a representation of a choice tree for a service, where the service includes an audio menu of available actions. A selection of an action displayed in the representation is received. The method also includes automatically navigating the audio menu in order to initiate the selected action. Apparatus and computer readable media are also described.
    Type: Grant
    Filed: November 2, 2009
    Date of Patent: April 12, 2016
    Assignee: International Business Machines Corporation
    Inventors: Peter J. Andrews, Alexander Faisman, Genady Grabarnik, Larisa Shwartz
  • Publication number: 20110103559
    Abstract: A method for voice browsing an integrated voice response server is described. The method includes visually displaying a representation of a choice tree for a service, where the service includes an audio menu of available actions. A selection of an action displayed in the representation is received. The method also includes automatically navigating the audio menu in order to initiate the selected action. Apparatus and computer readable media are also described.
    Type: Application
    Filed: November 2, 2009
    Publication date: May 5, 2011
    Inventors: Peter J. Andrews, Alexander Faisman, Genady Grabarnik, Larisa Shwartz
  • Patent number: 5047730
    Abstract: A bias current supply circuit (20) is provided which includes an initial current source comprising a FET (22) coupled to a current mirror circuit comprising a pair of BJTs (26 and 28). An active resistive element comprising a second FET (24) is included to stabilize an output current I.sub.0 with respect to ambient temperature variations and process variations.
    Type: Grant
    Filed: September 12, 1990
    Date of Patent: September 10, 1991
    Assignee: Texas Instruments Incorporated
    Inventors: Felicia M. James, Peter J. Andrews
  • Patent number: 4975632
    Abstract: A bias current supply circuit (20) is provided which includes an initial current source comprising a FET (22) coupled to a current mirror circuit comprising a pair of BJTs (26 and 28). An active resistive element comprising a second FET (24) is included to stabilize an output current I.sub.O with respect to ambient temperature variations and process variations.
    Type: Grant
    Filed: March 29, 1989
    Date of Patent: December 4, 1990
    Assignee: Texas Instruments Incorporated
    Inventors: Felicia M. James, Peter J. Andrews
  • Patent number: 4884039
    Abstract: A differential amplifier having input and output stages includes a linear offset operation circuit comprising sources providing a reference voltage and an offset correction voltage and a pair of transistors coupled for linear operation and responsive to the voltages for supplying differential related offset correction currents to the amplifier output stage for reducing offset characteristic of the amplifier stages and for reducing output noise and offset attributable to a noise component of the reference voltage source.
    Type: Grant
    Filed: September 9, 1988
    Date of Patent: November 28, 1989
    Assignee: Texas Instruments Incorporated
    Inventors: Lawrence A. King, Peter J. Andrews
  • Patent number: 4536835
    Abstract: A direct AC to AC supply converter in which the control of the bidirectional switches connecting each conductor of a polyphase input supply to each conductor of an output supply is effected by a data processor, the operation of the program of which is synchronized by interrupt with the input supply. The data processor calculates for each output phase 2 values representing pulse widths out of a repeating sequence of 3 (for three phase input and output supplies) and pulse generators produce 3 abutting width modulated pulses in a constant period much shorter than the periods of the supplies. The interrupt operates a software phase locked loop. The pulse generators include an interlock circuit ensuring that the width modulated pulses do not overlap and an overload detector responsive to the turn-on times of the switches. A default logic circuit responsive to hardward or software failure makes the width modulated pulses of equal duration.
    Type: Grant
    Filed: January 7, 1983
    Date of Patent: August 20, 1985
    Assignee: Texas Instruments Incorporated
    Inventor: Peter J. Andrews