Patents by Inventor Peter J. Camporese

Peter J. Camporese has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6629298
    Abstract: A method (and a system for using the method) for automating a slew rate analysis between two or more circuits on a semiconductor chip. The method includes the steps of: receiving as input one or more input parameters characterizing the physical medium through which the signal propagation occurs (the net) and the electrical characteristics of signals transmitted between the circuits; and providing as output one or more output parameters characterizing the appropriate solution for physical implementation of the circuit(s) and net(s) which satisfy the performance requirements of the system. The receiving step can comprise any one of: providing a hierarchical signal name cross-reference defining a name for the signal for a given hierarchy level of the circuits; providing a set of one or more boolean equations used to generate the one or more output parameters from the one or more input parameters; providing a physical design information for the circuits; and providing a timing information for the signals.
    Type: Grant
    Filed: November 10, 1999
    Date of Patent: September 30, 2003
    Assignee: International Business Machines Corporation
    Inventors: Peter J. Camporese, Adam R. Jatkowski, Leon J. Sigal, Patrick M. Williams
  • Patent number: 6618844
    Abstract: A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: September 9, 2003
    Assignee: International Business Machines Corporation
    Inventors: Allan H. Dansky, Wiren D. Becker, Howard H. Smith, Peter J. Camporese, Kwok Fai Eng, Dale E. Hoffman, Bhupindra Singh
  • Patent number: 6618843
    Abstract: A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: September 9, 2003
    Assignee: International Business Machines Corporation
    Inventors: Allan H. Dansky, Wiren D. Becker, Howard H. Smith, Peter J. Camporese, Kwok Fai Eng, Dale E. Hoffman, Bhupindra Singh
  • Patent number: 6546529
    Abstract: Deterministic evaluation of coupling noise voltage is a function of many physical and electrical parameters such as wiring level, widths, spacing, net topologies, drv impedance and slew rates. This evaluation requires electrical modeling and subsequent circuit simulation to assess the sensitivities of these parameters. These sensitivities can be categorized as coupling guidelines that can be directly linked through extracted physical design data. This invention discloses the development and implementation of a technique for using a coupling guideline table early in the design of an integrated circuit when all the parameters generally required for coupling noise voltage calculations are not available.
    Type: Grant
    Filed: October 2, 2000
    Date of Patent: April 8, 2003
    Assignee: International Business Machines Corporation
    Inventors: Allan H. Dansky, Michael A. Bowen, Peter J. Camporese, Alina Deutsch, Howard H. Smith
  • Patent number: 6487706
    Abstract: A method for partitioning wiring connecting individual physical elements of a VLSI chip of a hierarchical design having multiple levels, begins by defining a size for the chip of a hierarchical design, and then removing blocked areas, including clock and power grid areas leaving the wiring channels available for interconnecting the individual elements of the VLSI chip. A percentage of the available area is allocated for wiring levels for global and local wiring as parallel iterations for the global and local wiring proceed and modified as the parallel iterations for the global and local wiring progress. During the parallel iterative process the number of wires increases for the power grid area to prevent a signal wire from having an active wire on either side of the signal wire. In the interactive process, a vertical slice of wiring resources used for the space above a macro entity is defined and the macro entity is checked with the context of the VLSI chip physical design above it.
    Type: Grant
    Filed: August 30, 2000
    Date of Patent: November 26, 2002
    Assignee: International Business Machines Corporation
    Inventors: Keith G. Barkley, Peter J. Camporese, Kwok Fai Eng
  • Patent number: 6460169
    Abstract: A routing program length method for positioning unit pins in a hierarchically designed VLSI chip first identifies unit pin positions initially assigned in a hierarchical VLSI design that, if implemented, would increase the net length of the net of which the unit pins are a part. To identify unit pins, where the unit pin position assigned by the unit designer turns out to be a poor choice of position when the unit is integrated into the top level design, a “flat” file is created of the completed VLSI design with the units positioned on the chip, including their pin placements as assigned by the unit designers. The flat file includes not only top level unit data and unit-to-unit net data, but also macro data and macro net data integral to each unit design. The flat design data file is used to generate two pin logs; one pin log includes the Incremental lengths of each net including the incremental lengths associated with the unit pins (if any) assigned by the designers of the units.
    Type: Grant
    Filed: October 21, 1999
    Date of Patent: October 1, 2002
    Assignee: International Business Machines Corporation
    Inventors: Peter J. Camporese, Allan H. Dansky, Howard H. Smith
  • Patent number: 6415428
    Abstract: A method for identifying and positioning sub-optimally positioned unit pins in a hierarchically designed VSLI chip without modifying unit placement, comprising: generating a flat data file, generating a first pin log using the flat data file including data for unit pins and for macro pins of a net, generating a second pin log using the flat data file including data for macro pins of the net, determining a minimal net length using the first pin log and determining a minimum net length using the second pin log, calculating the difference between the minimal net length determined using the first ping log and the minimal net length determmed using the second pin log, identifying sub-optimally positioned unit pins by comparing the calculated difference to a threshold, and repositioning the identified sub-optimally positioned unit pins.
    Type: Grant
    Filed: October 21, 1999
    Date of Patent: July 2, 2002
    Assignee: International Business Machines Corporation
    Inventors: Peter J. Camporese, Allan H. Dansky, Howard H. Smith
  • Patent number: 6374394
    Abstract: A method for identifying unit pin positions initially assigned in a hierarchical VLSI design that, if implemented, would increase the net length of the net of which the unit pins are a part. To identify unit pins, where the unit pin position assigned by the unit designer turns out to be a poor choice of position when the unit is integrated into the top level design, a “flat” file is created of the completed VLSI design with the units positioned on the chip, including their pin placements as assigned by the unit designers. The flat file includes not only top level unit data and unit-to-unit net data, but also macro data and macro net data integral to each unit design. The flat design data file is used to generate two pin logs; one pin log includes the incremental lengths of each net including the incremental lengths associated with the unit pins (if any) assigned by the designers of the units.
    Type: Grant
    Filed: October 21, 1999
    Date of Patent: April 16, 2002
    Assignee: International Business Machines Corporation
    Inventors: Peter J. Camporese, Allan H. Dansky, Howard H. Smith
  • Publication number: 20020040463
    Abstract: A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.
    Type: Application
    Filed: June 29, 2001
    Publication date: April 4, 2002
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Allan H. Dansky, Wiren D. Becker, Howard H. Smith, Peter J. Camporese, Kwok Fai Eng, Dale E. Hoffman, Bhupindra Singh
  • Publication number: 20020040467
    Abstract: A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.
    Type: Application
    Filed: June 29, 2001
    Publication date: April 4, 2002
    Applicant: INTERNATION BUSINESS MACHINES CORPORATION
    Inventors: Allan H. Dansky, Wiren D. Becker, Howard H. Smith, Peter J. Camporese, Kwok Fai Eng, Dale E. Hoffman, Bhupindra Singh
  • Patent number: 6341365
    Abstract: A method (and a system for using the method) for placing a semiconductor circuit device between a driver and one or more receivers on the floor space of a chip. The method includes the steps of: determining respective distances between the driver and each of the one or more receivers; determining a shortest of the distances; determining midpoint along the shortest distance; determining whether the midpoint is predesignated to the floor space of one or more blocking semiconductor circuit devices; placing the repeater at the midpoint if the midpoint is not predesignated to the one or more blocking semiconductor circuit devices; and applying a backoff algorithm to incrementally back away from the midpoint to an optimal location, and placing the repeater at the optimal location, if the midpoint is predesignated to the one or more blocking semiconductor circuit devices.
    Type: Grant
    Filed: September 15, 1999
    Date of Patent: January 22, 2002
    Assignee: International Business Machines Corporation
    Inventors: Robert P. Dwyer, Peter J. Camporese
  • Patent number: 6323050
    Abstract: A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.
    Type: Grant
    Filed: October 2, 2000
    Date of Patent: November 27, 2001
    Assignee: International Business Machines Corporation
    Inventors: Allan H. Dansky, Wiren D. Becker, Howard H. Smith, Peter J. Camporese, Kwok Fai Eng, Dale E. Hoffman, Bhupindra Singh
  • Patent number: 6311313
    Abstract: An X-Y grid tree clock distribution network for distributing a clock signal across a VLSI chip. Tunable wiring tree networks are combined with an X-Y grid vertically and horizontally connecting all the tree end points. No drivers are necessary at connection points of the tree end points to the X-Y grid. The final X-Y grid distributes the clock signal close to every place it is needed, and reduces skew across local regions. A tuning method allows buffering of the clock signal, while minimizing both nominal clock skew and clock uncertainty. The tuned tree networks provide low skew even with variations in clock load density and non-ideal buffer placement, while minimizing the number of buffers needed. The tuning method first represents a total capacitance of one or more of clock pin loads and twig wiring as a clustered grid load. Next, a smoothing of the clustered grid loads approximates the effect of the X-Y grid.
    Type: Grant
    Filed: December 29, 1998
    Date of Patent: October 30, 2001
    Assignee: International Business Machines Corporation
    Inventors: Peter J. Camporese, Alina Deutsch, Timothy Gerard McNamara, Phillip John Restle, David Allan Webber
  • Patent number: 6205571
    Abstract: An X-Y grid tree clock distribution network for distributing a clock signal across a VLSI chip. Tunable wiring tree networks are combined with an X-Y grid vertically and horizontally connecting all the tree end points. No drivers are necessary at connection points of the tree end points to the X-Y grid. The final X-Y grid distributes the clock signal close to every place it is needed, and reduces skew across local regions. A tuning method allows buffering of the clock signal, while minimizing both nominal clock skew and clock uncertainty. The tuned tree networks provide low skew even with variations in clock load density and non-ideal buffer placement, while minimizing the number of buffers needed. The tuning method first represents a total capacitance of one or more of clock pin loads and twig wiring as a clustered grid load. Next, a smoothing of the clustered grid loads approximates the effect of the X-Y grid.
    Type: Grant
    Filed: December 29, 1998
    Date of Patent: March 20, 2001
    Assignee: International Business Machines Corporation
    Inventors: Peter J. Camporese, Alina Deutsch, Timothy Gerard McNamara, Phillip John Restle, David Allan Webber
  • Patent number: 5455931
    Abstract: A clock tuning system and method for a data processing system with enhanced timing failure diagnostics and unlayering capabilities. Both common and individual phase adjusting capabilities ensure programmable tuning of clock pulses distributed throughout a computer system, thereby facilitating isolation of timing margin failure to specific clock signals or enhancing system performance by shifting timing margin between logic paths. Both single-clock and dual-clock data processing are discussed, as well as clock tuning embodiments for each.
    Type: Grant
    Filed: November 19, 1993
    Date of Patent: October 3, 1995
    Assignee: International Business Machines Corporation
    Inventors: Peter J. Camporese, Patrick J. Meaney, Brian J. O'Leary, Richard F. Rizzolo