Abstract: In a multiprocessor system interconnected by a bus structure that provides communication and information transfers between the processor modules of the system, each processor broadcasts a central message to all the other processors of the system on a periodic basis. A processor module not receiving the control message from a sending processor module will assume the sending processor module has failed, and operate to take over the task of the failed processor module.

Abstract: In a multiprocessor system comprising a plurality of individual processor modules interconnected by a bus structure, including a bus controller, for providing communication between the processor modules, a method and apparatus for interprocessor communication includes one of the processor modules sending a request signal to the bus controller to request a transmission; the bus controller polling the processor modules to identify the requesting processor module; the requestor processor module responding to the poll with the identification of the receiver processor module; the bus controller interrogating the receiver processor module to determine its status (i.e., busy or available); and the bus controller then signaling transmission commencement.

Abstract: In a multiprocessor system of the type in which two or more separate processor modules are connected by an interprocessor bus dedicated exclusively to interprocessor communication for parallel processing, there is provided an input/output system having multiported device controllers connected to the multiprocessor system by input/output buses. Each device controller is shared by pairs of the processor modules, and includes logic that ensures that only one port is selected for access at a time.

Abstract: A multiprocessor system of the kind in which two or more separate processor modules are interconnected for parallel processing includes interprocessor buses dedicated exclusively to interprocessor communication. The multiprocessor system includes an input/output system having multi-port device controllers and input/output buses connecting each device controller for access by the input/output channels of at least two different processor modules. Each device controller includes logic which insures that only one port is selected for access at a time. An enable latch in each port dynamically disables that port from placing any signals on the related input/output bus in response to a failure of any portion of the device controller, and the enable latch is not responsive to the processor module for re-enabling the port.

Abstract: A multiprocessor system the kind in which two or more separate processor modules are interconnected for parallel processing. The multiprocessor system includes an input/output system having multi-port device controllers and input/output buses connecting each device controller for access by the input/output channels of at least two different processor modules.The multiprocessor system includes a distributed power supply system which insures non-stop operation of the remainder of the multiprocessor system in the event of a failure of a power supply for a part of the system. The distributed power supply system includes a separate power supply for each processor module and two separate power supplies for each device controller. A power interlock system and a method are provided for protection against data corruption.

Abstract: An input/output system for a processor of the kind in which a processor module has a central processing unit, a memory, an input/output channel, and a plurality of device controllers for controlling the transfer of data between the processor module and the peripheral devices includes a star poll connection in which each device controller is provided with a signalling means for signalling its identity in response to a poll operation, independently of other similarly connected device controllers such that any number of device controllers can be failed or powered off without affecting the polling of the other device controllers. The data lines in an input/output bus are used both to transmit data and to transmit signals to reduce the total number of lines needed to connect the device controllers to the channel in the star poll connection. The system is a fault tolerant system which includes an enable bit in the port of each device controller.

Abstract: A datapath system and protocol is disclosed in which data is transferred between a computer memory and one or more peripheral devices through device controllers, each of which includes a buffer, through periodic connection of the device controller to the channel. The system and protocol are structured to permit multiple device controllers to cooperatively interact on a single channel, without direct communication between device controllers. Each device controller monitors the level of stress on its buffer and at appropriate times presents a reconnect request to the channel, together with indica for permitting the channel to determine the priority of a particular request relative to other reconnect requests. The times at which a reconnect signal should be presented are determined by monitoring the level of information storage in the buffer and relating that level to a threshold level; both overfilling and overemptying are prevented.

Abstract: A multiprocessor system the kind in which two or more separate processor modules are interconnected for parallel processing includes two redundant interprocessor buses dedicated exclusively to interprocessor communication. Any processor module may send information to any other processor module by either bus.The multiprocessor system includes a memory system in which the memory of each processor module is divided into four logical address areas--user data, system data, user code and system code. The memory system includes a map which translates logical addresses to physical addresses and which coacts with the multiprocessor system to bring pages from secondary memory into primary main memory as required to implement a virtual memory system. The map also provides a protection function. It provides inherent protection among users in a multiprogramming environment, isolates programs from data and protects system programs from the actions of user programs.

Abstract: A multiprocessor system, the kind in which two or more separate processor modules are interconnected for two power supplies, provides the entire power for the device controller in the event the other power supply fails. The distributed power supply system permits any processor module or device controller to be powered down so that on-line maintenance can be performed in a power-off condition while the rest of the multiprocessor system is on-line and functional.The multiprocessor system includes a memory system in which the memory of each processor module is divided into four logical address areas--user data, system data, user code and system code. The memory system includes a map which translates logical addresses to physical addresses and which coacts with the multiprocessor system to bring pages from secondary memory into primary main memory as required to implement a virtual memory system. The map also provides a protection function.

Abstract: A multiprocessor system the kind in which two or more separate processor modules are interconnected for parallel processing includes two redundant interprocessor buses dedicated exclusively to interprocessor communication. Any processor module may send information to any other processor module by either bus. The buses are shared in use by the processor modules on a time-sharing basis. Use of each bus is controlled by a special bus controller.The multiprocessor system includes an input/output system having multi-port device controllers and input/output buses connecting each device controller for access by the input/output channels of at least two different processor modules. Each device controller includes logic which insures that only one port is selected for access at a time.The multiprocessor system includes a distributed power supply system which insures nonstop operation of the remainder of the multiprocessor system in the event of a failure of a power supply for a part of the system.