Patents by Inventor Peter J. Heyrman
Peter J. Heyrman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170060627Abstract: Optimized placement of virtual machines in a cloud environment is based on factors that include processor-memory affinity. A smart migration mechanism (SMM) predicts an optimization score for multiple permutations of placing virtual machines on a target system to create an optimal move list. The optimization score is a theoretical score calculated using dynamic platform optimization (DPO). The SMM may allow the user to set initial parameters and change the parameters to create potential changes lists. The move lists are ranked to allow the user to select the optimal change list to provide the best affinity, quickest fulfillment of requirements and least disruption for a given set of parameters.Type: ApplicationFiled: August 24, 2015Publication date: March 2, 2017Inventors: Daniel C. Birkestrand, Peter J. Heyrman, Edward C. Prosser
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Patent number: 9569364Abstract: Techniques are disclosed for prefetching cache lines. One technique includes dispatching a virtual processor and recording a first set of addresses associated with one or more cache lines used by the virtual processor. The technique also includes redispatching the virtual processor and recording a second set of addresses associated with one or more cache lines used by the virtual processor. The technique further includes comparing the first set of addresses with the second set of addresses to determine one or more common addresses between the first set and the second set. The technique includes placing the one or more common addresses into a memory. Finally, the technique includes redispatching the virtual processor.Type: GrantFiled: February 8, 2016Date of Patent: February 14, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Peter J. Heyrman, Bret R. Olszewski, Ram Raghavan
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Publication number: 20160212061Abstract: Workload, preferably as one or more partitions, is migrated from a source server to one or more target servers by computing a respective projected performance optimization for each candidate partition and target, the optimization being dependent on a projected processor-memory affinity resulting from migrating candidate workload to the candidate target, and selecting a target to receive a workload accordingly. A target may be pre-configured to receive a workload being migrated to it by altering the configuration parameters of at least one workload currently executing on the target according to the projected performance optimization.Type: ApplicationFiled: May 23, 2015Publication date: July 21, 2016Inventors: Daniel C. Birkestrand, Peter J. Heyrman, Paul F. Olsen
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Publication number: 20160212202Abstract: Workload, preferably as one or more partitions, is migrated from a source server to one or more target servers by computing a respective projected performance optimization for each candidate partition and target, the optimization being dependent on a projected processor-memory affinity resulting from migrating candidate workload to the candidate target, and selecting a target to receive a workload accordingly. A target may be pre-configured to receive a workload being migrated to it by altering the configuration parameters of at least one workload currently executing on the target according to the projected performance optimization.Type: ApplicationFiled: January 20, 2015Publication date: July 21, 2016Inventors: Daniel C. Birkestrand, Peter J. Heyrman, Paul F. Olsen
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Patent number: 9298651Abstract: In-memory accumulation of hardware counts in a computer system is carried out by continuously sending count values from full-speed hardware counter units to a memory controller. A sending unit periodically samples performance data from the hardware counter units, and transmits count values to a bus interface for an interconnection bus which communicates with the memory controller. The memory controller responsively updates an accumulated count value stored in system memory using the current count value, e.g., incrementing the accumulated count value. A count value can be sent with a pointer to a memory location and an instruction on how the location is to be updated. The instruction may be an atomic read-modify-write operation, and the memory controller can include a dedicated arithmetic logic unit to carry out that operation. A data harvester can then be used to harvest accumulated count values by reading them from a table in system memory.Type: GrantFiled: June 24, 2013Date of Patent: March 29, 2016Assignee: International Business Machines CorporationInventors: Peter J. Heyrman, Venkat R. Indukuru, Carl E. Love, Aaron C. Sawdey, Philip L. Vitale
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Patent number: 9164853Abstract: A method of a computer system recovering from a core re-initialization failure is described. The method may include automatically detect a core re-initialization failure during a core re-initialization process by a hypervisor. The hypervisor automatically determines whether the core re-initialization failure is a permanent failure. If the core re-initialization failure is a permanent failure, then automatically determine, by the hypervisor, which cores are re-initialized and which cores are indeterminate. Automatically allocate the re-initialized cores between one or more virtual machines by the hypervisor.Type: GrantFiled: March 13, 2013Date of Patent: October 20, 2015Assignee: International Business Machines CorporationInventors: Peter J. Heyrman, Stuart Z. Jacobs, David A. Larson
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Patent number: 9135126Abstract: A method of a computer system recovering from a core re-initialization failure is described. The method may include automatically detect a core re-initialization failure during a core re-initialization process by a hypervisor. The hypervisor automatically determines whether the core re-initialization failure is a permanent failure. If the core re-initialization failure is a permanent failure, then automatically determine, by the hypervisor, which cores are re-initialized and which cores are indeterminate. Automatically allocate the re-initialized cores between one or more virtual machines by the hypervisor.Type: GrantFiled: February 7, 2013Date of Patent: September 15, 2015Assignee: International Business Machines CorporationInventors: Peter J. Heyrman, Stuart Z. Jacobs, David A. Larson
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Patent number: 9043563Abstract: In a computer system that includes multiple nodes and multiple logical partitions, a dynamic partition manager computes current memory affinity and potential memory affinity to help determine whether a reallocation of resources between nodes may improve memory affinity for a logical partition or for the computer system. If so, the reallocation of resources is performed so memory affinity for the logical partition or computer system is improved. Memory affinity is computed relative to the physical layout of the resources according to a hardware domain hierarchy that includes a plurality of primary domains and a plurality of secondary domains.Type: GrantFiled: December 7, 2012Date of Patent: May 26, 2015Assignee: International Business Machines CorporationInventors: Daniel C. Birkestrand, Peter J. Heyrman, Wade B. Ouren, Edward C. Prosser
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Patent number: 9009421Abstract: In a computer system that includes multiple nodes and multiple logical partitions, a dynamic partition manager computes current memory affinity and potential memory affinity to help determine whether a reallocation of resources between nodes may improve memory affinity for a logical partition or for the computer system. If so, the reallocation of resources is performed so memory affinity for the logical partition or computer system is improved. Memory affinity is computed relative to the physical layout of the resources according to a hardware domain hierarchy that includes a plurality of primary domains and a plurality of secondary domains.Type: GrantFiled: November 13, 2012Date of Patent: April 14, 2015Assignee: International Business Machines CorporationInventors: Daniel C. Birkestrand, Peter J. Heyrman, Wade B. Ouren, Edward C. Prosser
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Publication number: 20140379953Abstract: In-memory accumulation of hardware counts in a computer system is carried out by continuously sending count values from full-speed hardware counter units to a memory controller. A sending unit periodically samples performance data from the hardware counter units, and transmits count values to a bus interface for an interconnection bus which communicates with the memory controller. The memory controller responsively updates an accumulated count value stored in system memory using the current count value, e.g., incrementing the accumulated count value. A count value can be sent with a pointer to a memory location and an instruction on how the location is to be updated. The instruction may be an atomic read-modify-write operation, and the memory controller can include a dedicated arithmetic logic unit to carry out that operation. A data harvester can then be used to harvest accumulated count values by reading them from a table in system memory.Type: ApplicationFiled: June 24, 2013Publication date: December 25, 2014Inventors: Peter J. Heyrman, Venkat R. Indukuru, Carl E. Love, Aaron C. Sawdey, Philip L. Vitale
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Publication number: 20140223108Abstract: This disclosure includes a method for managing hardware prefetch policy of a partition in a partitioned environment which includes dispatching a virtual processor on a physical processor of a first node, assigning a home memory partition of a memory of a second node to the virtual processor, determining whether the first node and the second node are different nodes, disabling hardware prefetch for the virtual processor when the first node and the second node are different nodes, and enabling hardware prefetch when the first node and the second node are the same physical node.Type: ApplicationFiled: February 7, 2013Publication date: August 7, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Peter J. Heyrman, Bret R. Olszewski
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Publication number: 20140223225Abstract: A method of a computer system recovering from a core re-initialization failure is described. The method may include automatically detect a core re-initialization failure during a core re-initialization process by a hypervisor. The hypervisor automatically determines whether the core re-initialization failure is a permanent failure. If the core re-initialization failure is a permanent failure, then automatically determine, by the hypervisor, which cores are re-initialized and which cores are indeterminate. Automatically allocate the re-initialized cores between one or more virtual machines by the hypervisor.Type: ApplicationFiled: February 7, 2013Publication date: August 7, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Peter J. Heyrman, Stuart Z. Jacobs, David A. Larson
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Publication number: 20140223233Abstract: A method of a computer system recovering from a core re-initialization failure is described. The method may include automatically detect a core re-initialization failure during a core re-initialization process by a hypervisor. The hypervisor automatically determines whether the core re-initialization failure is a permanent failure. If the core re-initialization failure is a permanent failure, then automatically determine, by the hypervisor, which cores are re-initialized and which cores are indeterminate. Automatically allocate the re-initialized cores between one or more virtual machines by the hypervisor.Type: ApplicationFiled: March 13, 2013Publication date: August 7, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Peter J. Heyrman, Stuart Z. Jacobs, David A. Larson
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Publication number: 20140223109Abstract: This disclosure includes a method for managing hardware prefetch policy of a partition in a partitioned environment which includes dispatching a virtual processor on a physical processor of a first node, assigning a home memory partition of a memory of a second node to the virtual processor, determining whether the first node and the second node are different nodes, disabling hardware prefetch for the virtual processor when the first node and the second node are different nodes, and enabling hardware prefetch when the first node and the second node are the same physical node.Type: ApplicationFiled: January 9, 2014Publication date: August 7, 2014Applicant: International Business Machines CorporationInventors: Peter J. Heyrman, Bret R. Olszewski
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Publication number: 20140136801Abstract: In a computer system that includes multiple nodes and multiple logical partitions, a dynamic partition manager computes current memory affinity and potential memory affinity to help determine whether a reallocation of resources between nodes may improve memory affinity for a logical partition or for the computer system. If so, the reallocation of resources is performed so memory affinity for the logical partition or computer system is improved. Memory affinity is computed relative to the physical layout of the resources according to a hardware domain hierarchy that includes a plurality of primary domains and a plurality of secondary domains.Type: ApplicationFiled: December 7, 2012Publication date: May 15, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel C. Birkestrand, Peter J. Heyrman, Wade B. Ouren, Edward C. Prosser
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Publication number: 20140136800Abstract: In a computer system that includes multiple nodes and multiple logical partitions, a dynamic partition manager computes current memory affinity and potential memory affinity to help determine whether a reallocation of resources between nodes may improve memory affinity for a logical partition or for the computer system. If so, the reallocation of resources is performed so memory affinity for the logical partition or computer system is improved. Memory affinity is computed relative to the physical layout of the resources according to a hardware domain hierarchy that includes a plurality of primary domains and a plurality of secondary domains.Type: ApplicationFiled: November 13, 2012Publication date: May 15, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel C. Birkestrand, Peter J. Heyrman, Wade B. Ouren, Edward C. Prosser
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Patent number: 8271989Abstract: The present invention provides a computer implemented method, data processing system, and computer program product for mapping and dispatching virtual processors in a data processing system having at least a first partition and a second partition. The data processing system runs a first partition on a virtual processor during a first timeslice. The data processing system identifies an at least one physical page used by the first partition and the second partition. The data processing system maps the at least one physical page to the first partition and the second partition. The data processing system determines a fitness value based on the mapping. The data processing system dispatches the Virtual processor to the second partition on a second timeslice based on the fitness value, wherein the second timeslice immediately succeeds after the first timeslice, whereby the at least one physical page remains in cache during at least the first timeslice and the second timeslice.Type: GrantFiled: February 7, 2008Date of Patent: September 18, 2012Assignee: International Business Machines CorporationInventors: Vaijayanthimala K. Anand, Peter J. Heyrman, Bret R. Olszewski
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Publication number: 20120102258Abstract: A method of dynamically reallocating memory affinity in a virtual machine after migrating the virtual machine from a source computer system to a destination computer system migrates processor states and resources used by the virtual machine from the source computer system to the destination computer system. The method maps memory of the virtual machine to processor nodes of the destination computer system. The method deletes memory mappings in processor hardware, such as translation lookaside buffers and effective-to-real address tables, for the virtual machine on the destination computer system. The method starts the virtual machine on the destination computer system in virtual real memory mode. A hypervisor running on the destination computer system receives a page fault and virtual address of a page for said virtual machine from a processor of the destination computer system and determines if the page is in local memory of the processor.Type: ApplicationFiled: October 22, 2010Publication date: April 26, 2012Applicant: International Business Machines CorporationInventors: David A. Hepkin, Peter J. Heyrman, Bret R. Olszewski
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Publication number: 20090204959Abstract: The present invention provides a computer implemented method, data processing system, and computer program product for mapping and dispatching virtual processors in a data processing system having at least a first partition and a second partition. The data processing system runs a first partition on a virtual processor during a first timeslice. The data processing system identifies an at least one physical page used by the first partition and the second partition. The data processing system maps the at least one physical page to the first partition and the second partition. The data processing system determines a fitness value based on the mapping. The data processing system dispatches the Virtual processor to the second partition on a second timeslice based on the fitness value, wherein the second timeslice immediately succeeds after the first timeslice, whereby the at least one physical page remains in cache during at least the first timeslice and the second timeslice.Type: ApplicationFiled: February 7, 2008Publication date: August 13, 2009Inventors: Vaijayanthimala K. Anand, Peter J. Heyrman, Bret R. Olszewski
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Patent number: 5991757Abstract: A data processing system includes at least one processor and data storage containing an array including N records having value-ordered entries. To find an entry matching a search value, W, a number of records to be searched, is set equal to N, and each of the W records is assigned to either a first set or a second set, where the first set includes X/2 of the W records and X is a smallest power of 2 equal to or greater than W. In response to a determination that the search value precedes the first record within the second set, a binary search of the first set of records is performed to identify a record including an matching entry. If the first entry of the first record within the second set matches the search value, the first record within the second set is identified.Type: GrantFiled: March 31, 1998Date of Patent: November 23, 1999Assignee: International Business Machines CorporationInventors: Stephen A. Dahl, John C. Endicott, Peter J. Heyrman, R. Karl Kirkman, Richard G. Mustain, Jon H. Peterson