Abstract: A class-D driver circuit includes a feedback loop including an input integrator stage, a switched modulator, and an output driver stage. A feedback resistor connects an output terminal of the output driver stage with an input node of the input integrator stage to provide a feedback current. The class-D driver circuit also includes a compensation circuit configured to provide a compensation current to an output node of the input integrator stage to relieve a slew rate limitation of the feedback loop, the compensation current having a magnitude based on the magnitude of the feedback current.

Abstract: A circuit for determining a slew rate of an input signal includes a first MOSFET, a second MOSFET, and a resistor coupled in series between a ground terminal and a power terminal. The resistor is coupled between the power terminal and the second MOSFET, and the first MOSFET is coupled between the second MOSFET and the ground. The second MOSFET is coupled to a bias circuit to provide a bias current. The circuit also includes a capacitor having a first terminal and a second terminal, the first terminal coupled to the input signal and the second terminal coupled to the gate terminal and the drain terminal of the first MOSFET. A current flowing through the MOSFET during changes in the input signal represents a slew rate of the input signal.

Abstract: In a clock frequency doubler, an input clock feeds into a digital programmable delay circuit, and an inverted input clock feeds into another digital programmable delay. The outputs of these digital programmable delay circuits are combined with the input clock and inverse clock through AND gates in order to generate clock pulses at both the rising and falling edge of the clock. These signals are combined using an OR gate to provide an output clock signal with a frequency that is double the frequency of the input clock signal. The values of the control bits for the digital programmable delay circuit are determined in a time-to-digital conversion (TDC) circuit that includes a Successive Approximation Register (SAR). For every cycle of the clock, the SAR circuit successively sets the programmable delay control bits and compares the delay circuit output with the input clock to determine the value of the control bits.

Abstract: A circuit for determining a slew rate of an input signal includes a first MOSFET, a second MOSFET, and a resistor coupled in series between a ground terminal and a power terminal. The resistor is coupled between the power terminal and the second MOSFET, and the first MOSFET is coupled between the second MOSFET and the ground. The second MOSFET is coupled to a bias circuit to provide a bias current. The circuit also includes a capacitor having a first terminal and a second terminal, the first terminal coupled to the input signal and the second terminal coupled to the gate terminal and the drain terminal of the first MOSFET. A current flowing through the MOSFET during changes in the input signal represents a slew rate of the input signal.

Abstract: A voltage regulator includes a delay chain having a plurality of delay elements, a thermometer to binary encoder coupled to multiple nodes in the delay chain to provide a first binary number that is indicative of an estimated delay of the delay chain, and a latch coupled to the thermometer to binary encoder to receive the binary number. The voltage regulator also includes a signal processing circuit for providing a control signal indicative of a difference between the first binary number with a second binary number that represents a target delay, and a voltage control circuit coupled to the signal processing circuit for providing an output voltage based on the control signal from the processing circuit.

Abstract: A voltage regulator includes a delay chain having a plurality of delay elements, a thermometer to binary encoder coupled to multiple nodes in the delay chain to provide a first binary number that is indicative of an estimated delay of the delay chain, and a latch coupled to the thermometer to binary encoder to receive the binary number. The voltage regulator also includes a signal processing circuit for providing a control signal indicative of a difference between the first binary number with a second binary number that represents a target delay, and a voltage control circuit coupled to the signal processing circuit for providing an output voltage based on the control signal from the processing circuit.

Abstract: An audio system has a first channel for receiving a first input signal and driving a first speaker and a second channel for receiving a second input signal and driving a second speaker. A first feedforward circuit couples an input of the second channel circuit to an input of the first channel circuit. A second feedforward circuit couples an input of the first channel circuit to an input of the second channel circuit. Circuit parameters of the first and the second feedforward circuits are determined such that a first detected output signal is zero when the first input signal is non-zero and the second input signal is zero, and a second detected output signal is zero when the second input signal is non-zero and the first input signal is zero. The audio system is configured to operate using the determined circuit parameters for the first and the second feedforward circuits.

Abstract: An integrated audio signal processing circuit is described for reducing crosstalk noise in an integrated headset switch for a headset having two speakers, a microphone sharing a common ground. The audio signal processing circuit includes two audio amplifiers and also has two terminals configured to be either a microphone connection terminal or a headset ground connection terminal, respectively, depending on the type of the headset. An audio amplifier reference node is coupled to inputs of the audio amplifiers. The audio signal processing circuit has a first switch device responsive to a headset ground selection signal and configured to connect the audio amplifier reference node to the detected headset ground connection terminal. The audio signal processing circuit also has a second switch device responsive to the headset ground selection signal and configured to couple the detected headset ground connection terminal to a ground terminal of the audio processing circuit.

Abstract: An integrated audio signal processing circuit is described for reducing crosstalk noise in an integrated headset switch for a headset having two speakers, a microphone sharing a common ground. The audio signal processing circuit includes two audio amplifiers and also has two terminals configured to be either a microphone connection terminal or a headset ground connection terminal, respectively, depending on the type of the headset. An audio amplifier reference node is coupled to inputs of the audio amplifiers. The audio signal processing circuit has a first switch device responsive to a headset ground selection signal and configured to connect the audio amplifier reference node to the detected headset ground connection terminal. The audio signal processing circuit also has a second switch device responsive to the headset ground selection signal and configured to couple the detected headset ground connection terminal to a ground terminal of the audio processing circuit.

Abstract: An audio system has a first channel for receiving a first input signal and driving a first speaker and a second channel for receiving a second input signal and driving a second speaker. A first feedforward circuit couples an input of the second channel circuit to an input of the first channel circuit. A second feedforward circuit couples an input of the first channel circuit to an input of the second channel circuit. Circuit parameters of the first and the second feedforward circuits are determined such that a first detected output signal is zero when the first input signal is non-zero and the second input signal is zero, and a second detected output signal is zero when the second input signal is non-zero and the first input signal is zero. The audio system is configured to operate using the determined circuit parameters for the first and the second feedforward circuits.

Abstract: An integrated circuit (IC) chip has a class D PWM (pulse width modulation) amplifier configured for generating first and second PWM signals. The class-D PWM modulator includes a differential output driver configured for driving a first and a second output signals in response to the first and the second PWM signals. A clipping detection circuit is configured to turn on a clipping indication signal when one or both of the first PWM signal and the second PWM signal maintain the same state between two consecutive edges of the oscillator clock signal. The clipping detection circuit is also configured to turn off the clipping indication signal when both the first PWM signal and the second PWM signal change states between two consecutive edges of the oscillator clock signal.

Abstract: An integrated circuit (IC) chip has a class D PWM (pulse width modulation) amplifier configured for generating first and second PWM signals. The class-D PWM modulator includes a differential output driver configured for driving a first and a second output signals in response to the first and the second PWM signals. A clipping detection circuit is configured to turn on a clipping indication signal when one or both of the first PWM signal and the second PWM signal maintain the same state between two consecutive edges of the oscillator clock signal. The clipping detection circuit is also configured to turn off the clipping indication signal when both the first PWM signal and the second PWM signal change states between two consecutive edges of the oscillator clock signal.

Abstract: An audio system includes a speaker and a class D amplifier with a class-D PWM (pulse width modulation) modulator configured for generating first and second PWM signals forming a differential signal with three differential output levels with three differential output levels. The class-D amplifier also has a differential output driver configured for driving a first and a second output signals onto a first and a second output terminals in response to the first and the second PWM signals, wherein the first and the second output signals form a differential output signal having three differential output levels. An inverse common-mode signal generator is coupled to first and second output signals for providing an inverse common-mode signal. The audio system also includes one or more output terminals for providing the inverse common mode signal, and further includes a wire or a trace on a PCB (printed circuit board).

Abstract: An audio system includes a speaker and a class D amplifier with a class-D PWM (pulse width modulation) modulator configured for generating first and second PWM signals, each with three differential output levels. The class-D amplifier also has a differential output driver configured for driving a first and a second output signals onto a first and a second output terminals in response to the first and the second PWM signals, wherein each of the first and the second output signals has three differential output levels. An inverse common-mode signal generator is coupled to first and second output signals for providing an inverse common-mode signal. The audio system also includes one or more output terminals for providing the inverse common mode signal, and further includes a wire or a trace on a PCB (printed circuit board) inverse common mode signal.

Abstract: Programmable plain old telephone line impedance matching circuits that provide an accurate, integrated programmable termination and source impedance for a telephone line interface circuit (SLIC). The accurate matching of this programmable termination and source impedance with the termination impedance of the 2 Wire connection eliminates signal reflections on this connection and therefore removes the echo, which echo can lead to reduced signal quality in packetized VOIP systems. The programmable integrated impedance matching circuits of this invention use a programmable time continuous amplifier preferably in combination with a double sampling programmable switched capacitor feedback stage (sampling twice per clock cycle by sampling on the positive and negative phases of a non-overlapping clock cycle).

Abstract: Programmable plain old telephone line impedance matching circuits that provide an accurate, integrated programmable termination and source impedance for a telephone line interface circuit (SLIC). The accurate matching of this programmable termination and source impedance with the termination impedance of the 2 Wire connection eliminates signal reflections on this connection and therefore removes the echo, which echo can lead to reduced signal quality in packetized VOIP systems. The programmable integrated impedance matching circuits of this invention use a programmable time continuous amplifier preferably in combination with a double sampling programmable switched capacitor feedback stage (sampling twice per clock cycle by sampling on the positive and negative phases of a non-overlapping clock cycle).

Abstract: A text-to-speech conversion system that includes a first module to convert text into words, a second module to convert words into phonemes, a third module to map phonemes to sound units, and a storage unit to store speech representations for a library of sound units. The first, second, and third modules and the storage unit are implemented within a single integrated circuit to reduce size and cost. The system typically further includes a ROM to store the codes for the modules, a RAM to store the text and intermediate results, a processor to execute the codes for the modules, a control module to direct the operation of the first, second, and third modules. The storage unit may be implemented with a multi-level, non-volatile analog storage array and may be programmed with a new library of speech representations by a programming module.

Abstract: A noise reduction apparatus (and methods). The apparatus has a housing and a processing device coupled to the housing. A sensor is coupled to the processing device and may be adapted to the housing. The sensor is adapted to determine a noise signal. A programmable memory is coupled to the processing device. The programmable memory device comprises 1 to N periodic frequency band limited noise wave shapes that are capable of reducing an intensity level of the noise signal. The apparatus also has an output device that is coupled to the processing device. The output device is adapted to output the periodic frequency band limited noise wave shape that is capable of reducing the intensity level of the noise signal.

Abstract: An apparatus and method for achieving accurate temperature-invariant sampling frequencies in a device, such as, a multiple message non-volatile multilevel analog signal recording and playback system is described. An oscillator is used to generate an oscillation frequency. A bandgap voltage generator generates a zero temperature coefficient voltage reference (V(OTC)) that is independent of temperature. This V(OTC) is applied to the oscillator. A variable temperature coefficient voltage (V(TC)) that compensates for temperature coefficient variations of a resistor to which V(TC) is applied produces a stable oscillator current Iosc. Therefore, the stable oscillator current Iosc is likewise independent of the temperature coefficient variations of the resistor. The stable oscillator current Iosc is applied to the oscillator such that the oscillator generates a stable temperature-invariant oscillation frequency.

Abstract: The present invention is a method and apparatus to program a flash memory cell in an analog storage array. A read circuit reads a cell voltage of a flash memory cell. A comparator compares the read cell voltage with an input voltage representing an analog signal. The comparator generates first and second comparison results. A programming circuit generates a first program pulse corresponding to a first amplitude to iteratively program the flash memory cell based on the first comparison result. The programming circuit generates a second program pulse corresponding to a second amplitude less than the first amplitude to iteratively program the flash memory cell based on the first and second comparison results.