Patents by Inventor Peter J. Hopper

Peter J. Hopper has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8338913
    Abstract: The inductance of an inductor is increased by forming a conductive wire to have a serpentine shape that weaves through a ferromagnetic core that has a number of segments that are connected together in a serpentine shape where each segment of the ferromagnetic core also has a number of sections that are connected together in a serpentine shape.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: December 25, 2012
    Assignee: National Semiconductor Corporation
    Inventors: Peter Smeys, Andrei Papou, Peter J. Hopper
  • Patent number: 8324603
    Abstract: Methods and structures provide galvanic isolation for electrical systems using a wide oxide filled trench, and that allows power across the system divide with a transformer, and that transmits data at a high baud rate using an optical link. The system solution allows the integration of all of these elements onto a single semiconductor substrate in contrast to currently available galvanic isolation systems that require multiple individual silicon die that are connected by wire bonds and are relatively slow.
    Type: Grant
    Filed: August 24, 2010
    Date of Patent: December 4, 2012
    Assignee: National Semiconductor Corporation
    Inventors: William French, Peter J. Hopper, Vladislav Vashchenko, Philipp Lindorfer
  • Patent number: 8303484
    Abstract: A self-propelled robotic device moves through bodily and other passageways by inflating regions of an overlying bladder along the length of the robotic device in a sequence that imparts motion to the device. The regions of the overlying bladder are inflated by energizing a plurality of coils, which are surrounded by a ferrofluid, in a sequence. The ferrofluid responds to the magnetic field created by an energized coil by creating a bulge in the side wall of the overlying bladder.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: November 6, 2012
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Philipp Lindorfer, William French, Visvamohan Yegnashankaran
  • Publication number: 20120273881
    Abstract: A lateral DMOS transistor formed on a silicon-on-insulator (SOI) structure has a higher breakdown voltage that results from a cavity that is formed in the bulk region of the SOI structure. The cavity exposes a portion of the bottom surface of the insulator layer of the SOI structure that lies directly vertically below the drift region of the DMOS transistor.
    Type: Application
    Filed: April 26, 2011
    Publication date: November 1, 2012
    Inventors: William French, Vladislav Vashchenko, Richard Wendell Foote, JR., Alexei Sadovnikov, Punit Bhola, Peter J. Hopper
  • Publication number: 20120261753
    Abstract: A DMOS transistor with a lower on-state drain-to-source resistance and a higher breakdown voltage utilizes a slanted super junction drift structure that lies along the side wall of an opening with the drain region at the bottom of the opening and the source region near the top of the opening.
    Type: Application
    Filed: April 13, 2011
    Publication date: October 18, 2012
    Inventors: Peter J. Hopper, Alexei Sadovnikov, William French, Erika Mazotti, Richard Wendell Foote, JR., Punit Bhola, Vladislav Vashchenko
  • Patent number: 8274129
    Abstract: A method includes forming a transistor device on a first side of a semiconductor-on-insulator structure. The semiconductor-on-insulator structure includes a substrate, a dielectric layer, and a buried layer between the substrate and the dielectric layer. The method also includes forming a conductive plug through the semiconductor-on-insulator structure. The conductive plug is in electrical connection with the transistor device. The method further includes forming a field plate on a second side of the semiconductor-on-insulator structure, where the field plate is in electrical connection with the conductive plug. The transistor device could have a breakdown voltage of at least 600V, and the field plate could extend along at least 40% of a length of the transistor device.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: September 25, 2012
    Assignee: National Semiconductor Corporation
    Inventors: William French, Peter Smeys, Peter J. Hopper, Peter Johnson
  • Publication number: 20120228480
    Abstract: An optically-controlled shunt (OCS) circuit includes a switch and a light sampler. The light sampler is coupled to the switch and is configured to sample light at a photovoltaic (PV) cell corresponding to the OCS circuit and to turn on the switch when the sampled light comprises insufficient light for the PV cell. The light sampler may also be configured to turn off the switch when the sampled light comprises sufficient light for the PV cell. The light sampler may further be configured to partially turn on the switch when the sampled light comprises adequate light for the PV cell and to turn off the switch when the sampled light comprises full light for the PV cell. The switch could include a transistor, and the light sampler could include a photodiode.
    Type: Application
    Filed: March 7, 2011
    Publication date: September 13, 2012
    Applicant: NATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Reda R. Razouk, Peter J. Hopper
  • Publication number: 20120217610
    Abstract: A bonded semiconductor structure is formed in a method that first forms a female semiconductor structure with pyramid-shaped openings and a male semiconductor structure with pyramid-shaped projections, and then inserts the projections into the openings to align the male semiconductor structure to the female semiconductor structure for bonding.
    Type: Application
    Filed: February 28, 2011
    Publication date: August 30, 2012
    Inventors: Peter J. Hopper, Peter Johnson, Luu Nguyen, Peter Smeys
  • Publication number: 20120175676
    Abstract: A photodetector detects the absence or presence of light by detecting a change in the inductance of a coil. The magnetic field generated when a current flows through the coil passes through an electron-hole generation region. Charged particles in the electron-hole generation region come under the influence of the magnetic field, and generate eddy currents whose magnitudes depend on whether light is absent or present. The eddy currents generate a magnetic field that opposes the magnetic field generated by current flowing through the coil.
    Type: Application
    Filed: January 11, 2011
    Publication date: July 12, 2012
    Inventors: Ann Gabrys, Peter J. Hopper, William French, Kyuwoon Hwang
  • Patent number: 8212320
    Abstract: In an ESD clamp formed in a SOI process, voltage tolerance is increased by introducing multiple blocking junctions between the anode and cathode of the device.
    Type: Grant
    Filed: March 15, 2006
    Date of Patent: July 3, 2012
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Peter J. Hopper
  • Publication number: 20120161294
    Abstract: Multiple wafers that each has multiple high-precision circuits and corresponding trim control circuits are batch trimmed in a process where each wafer is formed to include openings that expose trimmable circuit elements that are internal to the circuitry of the high-precision circuits. The high-precision circuits and trim control circuits are electrically activated during the trimming phase by metal traces that run along the saw streets. The method attaches a wafer contact structure to each wafer to electrically activate the metal traces. The method places the wafers with the wafer contact structures into a solution where the exposed trimmable circuit elements are electroplated or anodized when the actual output voltage of a high-precision circuit does not match the predicted output voltage of the high-precision circuit.
    Type: Application
    Filed: December 24, 2010
    Publication date: June 28, 2012
    Inventors: Peter J. Hopper, Peter Johnson, Peter Smeys, William French
  • Publication number: 20120154956
    Abstract: In a power device such as an NLDMOS power array comprising multiple NLDMOS devices, the gates of which are driven by a driver, self protection against overvoltage events is implemented by providing a high side pull-up avalanche diode connected to at least some of the gates of the NLDMOS devices.
    Type: Application
    Filed: December 17, 2010
    Publication date: June 21, 2012
    Inventors: Vladislav Vashchenko, Peter J. Hopper
  • Publication number: 20120112296
    Abstract: The inductance of an inductor is increased by forming a conductive wire to have a serpentine shape that weaves through a ferromagnetic core that has a number of segments that are connected together in a serpentine shape where each segment of the ferromagnetic core also has a number of sections that are connected together in a serpentine shape.
    Type: Application
    Filed: November 10, 2010
    Publication date: May 10, 2012
    Inventors: Peter Smeys, Andrei Papou, Peter J. Hopper
  • Publication number: 20120104548
    Abstract: A semiconductor capacitor with large area plates and a small footprint is formed on a semiconductor wafer by forming an opening in the wafer, depositing a first metal atoms through a first shadow mask that lies spaced apart from the wafer to form a first metal layer in the opening, a dielectric layer on the first metal layer, and a second metal atoms through a second shadow mask that lies spaced apart from the wafer to form a second metal layer on the dielectric layer.
    Type: Application
    Filed: November 2, 2010
    Publication date: May 3, 2012
    Inventors: Peter J. Hopper, William French
  • Publication number: 20120091501
    Abstract: In a DIAC-like device that includes an n+ and a p+ region connected to the high voltage node, and an n+ and a p+ region connected to the low voltage node, at least two MOS devices are formed between the n+ and p+ region connected to the high voltage node, and the n+ and p+ region connected to the low voltage node.
    Type: Application
    Filed: October 18, 2010
    Publication date: April 19, 2012
    Inventors: Vladislav Vashchenko, Antonio Gallerano, Peter J. Hopper
  • Publication number: 20120060587
    Abstract: A semiconductor-based gas detector enhances the collection of gas molecules and also provides a self-contained means for removing collected gas molecules by utilizing one or more electric fields to transport the gas molecules to and away from a metallic material that has a high permeability to the gas molecules.
    Type: Application
    Filed: September 13, 2010
    Publication date: March 15, 2012
    Inventors: Jeffrey A. Babcock, Peter J. Hopper, Yuri Mirgorodski
  • Patent number: 8130067
    Abstract: A semiconductor transformer provides high frequency operation by forming the primary windings of the transformer around a section of magnetic material that has a hard axis that lies substantially parallel to the direction of the magnetic field generated by the primary windings. The core can also be formed to have a number of sections where the magnetic flux follows the hard axis through each section of the core.
    Type: Grant
    Filed: May 11, 2010
    Date of Patent: March 6, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Dok Won Lee, Peter Smeys, Anuraag Mohan, Peter J. Hopper
  • Patent number: 8098121
    Abstract: A MEMS magnetic flux switch is fabricated as a ferromagnetic core. The core includes a center cantilever that is fabricated as a free beam that can oscillate at a resonant frequency that is determined by its mechanical and material properties. The center cantilever is moved by impulses applied by an associated motion oscillator, which can be magnetic or electric actuators.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: January 17, 2012
    Assignee: National Semiconductor
    Inventors: Peter J Hopper, Trevor Niblock, Peter Johnson, Vladislav Vashchenko
  • Publication number: 20120002377
    Abstract: An integrated circuit die system comprises a first integrated circuit die, a second integrated circuit die and a transformer formed on a dielectric (e.g., quartz) substrate and electrically connected between the first integrated circuit die and the second integrated circuit die to provide galvanic isolation therebetween.
    Type: Application
    Filed: June 30, 2010
    Publication date: January 5, 2012
    Inventors: William French, Peter J. Hopper, Peter Smeys, Ann Gabrys, David I. Anderson
  • Patent number: 8081494
    Abstract: In a grid-tie inverter, the DC input is phase and pulse-width modulated to define multiple phase shifted voltage pulses with the width of each pulse being modulated according to the grid AC amplitude for the corresponding portion of the AC phase.
    Type: Grant
    Filed: December 8, 2008
    Date of Patent: December 20, 2011
    Assignee: National Semiconductor Corporation
    Inventor: Peter J. Hopper