Abstract: A system provides communication between a plurality of cores in an integrated circuit. The system comprises a circular segmented bus operatively connected to each of the cores for transferring data between the plurality of cores. An arbiter arbitrates which of the plurality of cores can transmit data at any given time.

Abstract: A system and method for dynamically altering a clock speed of a clock signal used for timing of data signal transmissions and receptions within an integrated circuit (IC) device. The system includes a clock generator circuit for providing a clock signal used for timing of data signal transmission and reception within the IC; a monitoring circuit for receiving data transmissions generated at different clock speeds and detecting when a data transmission fail point is achieved at a particular clock speed; and, a device for adjusting the clock speed according to a maximum speed allowed for the IC that avoids the data transmission fail point.

Abstract: A method, program product, and design tool for automatic transmission line selection in application specific integrated circuits. The method includes: determining route paths between blocks of an application specific integrated circuit; scanning the route paths for transmission line replacement candidates; and, for each transmission line replacement candidate, automatically selecting a buffered wire or a transmission line to implement the route path.

Abstract: A method, program product, and design tool for automatic transmission line selection in application specific integrated circuits. The method includes: determining route paths between blocks of an application specific integrated circuit; scanning the route paths for transmission line replacement candidates; and, for each transmission line replacement candidate, automatically selecting a buffered wire or a transmission line to implement the route path.

Abstract: A system and method for dynamically altering a clock speed of a clock signal used for timing of data signal transmissions and receptions within an integrated circuit (IC) device. The system includes a clock generator circuit for providing a clock signal used for timing of data signal transmission and reception within the IC; a monitoring circuit for receiving data transmissions generated at different clock speeds and detecting when a data transmission fail point is achieved at a particular clock speed; and, a device for adjusting the clock speed according to a maximum speed allowed for the IC that avoids the data transmission fail point.

Abstract: A system provides communication between a plurality of cores in an integrated circuit. The system comprises a circular segmented bus operatively connected to each of the cores for transferring data between the plurality of cores. An arbiter arbitrates which of the plurality of cores can transmit data at any given time.

Abstract: A driver circuit provides for selectively changing the state of an output signal, such as a pre-charged dynamic bus signal. The circuit detects whether or not the data is the opposite state as the pre-charged bus signal, and if so, it drives the bus to the appropriate state. The output from the circuit is self-timed when data can be driven onto the bus as soon as data is valid, i.e., data propagates from the input of the circuit to the bus without depending on a clock or other timing edge.