Abstract: Aspects of the present disclosure relate to techniques for reducing skew in an integrated device, such as a CMOS imaging device. In some aspects, multiple pixels of an integrated circuit may be configured to receive a same control signal and conduct charge carriers responsive to the control signal substantially at the same time. In some aspects, an integrated circuit may have modulated charge transfer channel voltage thresholds, such as by having different charge transfer channel lengths, and/or a doped portion configured to set a voltage threshold for charge transfer. In some aspects, an integrated circuit may have a via structure having a plurality of vias extending between continuous portions of at least two metal layers. In some aspects, an integrated circuit may include a row of pixels and a voltage source configured to provide a voltage to bias a semiconductor substrate of the integrated circuit along the row of pixels.

Abstract: Aspects of the present disclosure relate to techniques for reducing skew in an integrated device, such as a CMOS imaging device. In some aspects, multiple pixels of an integrated circuit may be configured to receive a same control signal and conduct charge carriers responsive to the control signal substantially at the same time. In some aspects, an integrated circuit may have modulated charge transfer channel voltage thresholds, such as by having different charge transfer channel lengths, and/or a doped portion configured to set a voltage threshold for charge transfer. In some aspects, an integrated circuit may have a via structure having a plurality of vias extending between continuous portions of at least two metal layers. In some aspects, an integrated circuit may include a row of pixels and a voltage source configured to provide a voltage to bias a semiconductor substrate of the integrated circuit along the row of pixels.

Abstract: Aspects of the present disclosure relate to techniques for reducing skew in an integrated device, such as a CMOS imaging device. In some aspects, multiple pixels of an integrated circuit may be configured to receive a same control signal and conduct charge carriers responsive to the control signal substantially at the same time. In some aspects, an integrated circuit may have modulated charge transfer channel voltage thresholds, such as by having different charge transfer channel lengths, and/or a doped portion configured to set a voltage threshold for charge transfer. In some aspects, an integrated circuit may have a via structure having a plurality of vias extending between continuous portions of at least two metal layers. In some aspects, an integrated circuit may include a row of pixels and a voltage source configured to provide a voltage to bias a semiconductor substrate of the integrated circuit along the row of pixels.

Abstract: Aspects of the present disclosure relate to techniques for reducing skew in an integrated device, such as a CMOS imaging device. In some aspects, multiple pixels of an integrated circuit may be configured to receive a same control signal and conduct charge carriers responsive to the control signal substantially at the same time. In some aspects, an integrated circuit may have modulated charge transfer channel voltage thresholds, such as by having different charge transfer channel lengths, and/or a doped portion configured to set a voltage threshold for charge transfer. In some aspects, an integrated circuit may have a via structure having a plurality of vias extending between continuous portions of at least two metal layers. In some aspects, an integrated circuit may include a row of pixels and a voltage source configured to provide a voltage to bias a semiconductor substrate of the integrated circuit along the row of pixels.

Abstract: Embodiments for single-ended tri-level encoding and/or decoding of data are disclosed.

Abstract: The invention provides for an input/output circuit in a CMOS integrated circuit which can withstand pad voltages which are higher than the supply voltages for the integrated circuit. The input/output circuit has a pair of first polarity-type transistors which is connected in series between a first supply voltage terminal and the input/output pad, and a pair of second polarity-type transistors which is connected in series between a second supply voltage terminal and the pad. Responsive to a disable control signal, one of the first polarity-type and one of the second polarity-type transistors are turned off. Switch circuitry is connected between the pad and a gate of a second transistor of the second polarity-type transistor pair.

Abstract: A comparator circuit providing for improved symmetry of operation. The circuit includes two delay paths to facilitate rising and falling input transitions. Such paths are made up of an equal number and type of current mirrors. The circuit also includes an input differential pair wherein both delay paths are coupled to a single transistor of the pair.

Abstract: The invention provides for an input/output circuit in a CMOS integrated circuit which can withstand pad voltages which are higher than the supply voltages for the integrated circuit. The input/output circuit has a pair of first polarity-type transistors which is connected in series between a first supply voltage terminal and the input/output pad, and a pair of second polarity-type transistors which is connected in series between a second supply voltage terminal and the pad. Responsive to a disable control signal, one of the first polarity-type and one of the second polarity-type transistors are turned off. Switch circuitry is connected between the pad and a gate of a second transistor of the second polarity-type transistor pair.

Abstract: A graphics subsystem converts a first graphics data stream for display on a computer monitor having a first refresh rate into a second graphics data stream for a television monitor having a second, slower refresh rate. The graphics subsystem has a first memory for storing one horizontal scan line of pixel data and a second memory for storing one half of a horizontal scan line of pixel data. Multiplexers direct data to a first summing circuit from an input port and from the first memory itself, so that a first horizontal line of input pixel data is initially stored in the first memory and a second horizontal line of input pixel data is combined with the first horizontal line of data by the first summing circuit, and the resulting combined pixel data is stored in back into the first memory. A controller sends the combined pixel data from the first memory to a second summing circuit while a next horizontal line of input pixel data is received.