Patents by Inventor Peter J. Lindgren
Peter J. Lindgren has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9171778Abstract: A method and a semiconductor device are provided. The semiconductor device includes a partial via etched in a stacked structure and a trough above the partial via. The method includes performing thick wiring using selective etching while etching the partial via to an etch stop layer.Type: GrantFiled: January 28, 2014Date of Patent: October 27, 2015Assignee: GLOBALFOUNDRIES U.S. 2 LLCInventors: Douglas D. Coolbaugh, Keith E. Downes, Peter J. Lindgren, Anthony K. Stamper
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Patent number: 8872281Abstract: A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate. The trench is subsequently filled with a middle-of-line (MOL) dielectric. A contact via may be formed on the trench contact silicide. The trench contact silicide may be formed through a single silicidation reaction with a metal layer or through multiple silicidation reactions with multiple metal layers.Type: GrantFiled: August 9, 2012Date of Patent: October 28, 2014Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Jeffrey B. Johnson, Peter J. Lindgren, Xuefeng Lie, James S. Nakos, Bradley A. Omer, Robert M. Rassel, David C. Sheridan
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Publication number: 20140239498Abstract: A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate. The trench is subsequently filled with a middle-of-line (MOL) dielectric. A contact via may be formed on the trench contact silicide. The trench contact silicide may be formed through a single silicidation reaction with a metal layer or through multiple silicidation reactions with multiple metal layers.Type: ApplicationFiled: August 9, 2012Publication date: August 28, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Douglas D. Coolbaugh, Jeffrey B. Johnson, Peter J. Lindgren, Xuefeng Liu, James S. Nakos, Bradley A. Orner, Robert M. Rassel, David C. Sheridan
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Patent number: 8753950Abstract: A method and semiconductor device. In the method, at least one partial via is etched in a stacked structure and a border is formed about the at least one partial via. The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer.Type: GrantFiled: March 28, 2012Date of Patent: June 17, 2014Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Keith E. Downes, Peter J. Lindgren, Anthony K. Stamper
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Publication number: 20140164281Abstract: The various embodiments of the invention provide a data processing system and method, for applications such as marketing campaign management, speech recognition and signal processing. An exemplary system embodiment includes a first data repository adapted to store a plurality of entity and attribute data; a second data repository adapted to store a plurality of entity linkage data; a metadata data repository adapted to store a plurality of metadata modules, with a first metadata module having a plurality of selectable parameters, received through a control interface, and having a plurality of metadata linkages to a first subset of metadata modules; and a multidimensional data structure. The control interface may modify the plurality of selectable parameters in response to received control information.Type: ApplicationFiled: July 11, 2013Publication date: June 12, 2014Inventors: Nevzat Hurkan Balkir, Marc Louis Gutchell, Peter J. Lindgren, Eric Michael Tagliere
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Patent number: 8748207Abstract: Structures having a hybrid MEMS RF switch and method of fabricating such structures using existing wiring layers of a device is provided. The method of manufacturing a MEMS switch includes forming a forcing electrode from a lower wiring layer of a device and forming a lower electrode from an upper wiring layer of the device. The method further includes forming a flexible cantilever arm over the forcing electrode and the lower electrode such that upon application of a voltage to the forcing electrode, the flexible cantilever arm will contact the lower electrode to close the MEMS switch.Type: GrantFiled: May 10, 2013Date of Patent: June 10, 2014Assignee: International Business Machines CorporationInventors: Peter J. Lindgren, Anthony K. Stamper
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Publication number: 20140151899Abstract: A method and a semiconductor device are provided. The semiconductor device includes a partial via etched in a stacked structure and a trough above the partial via. The method includes performing thick wiring using selective etching while etching the partial via to an etch stop layer.Type: ApplicationFiled: January 28, 2014Publication date: June 5, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Douglas D. COOLBAUGH, Keith E. DOWNES, Peter J. LINDGREN, Anthony K. STAMPER
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Patent number: 8722508Abstract: A low harmonic radio-frequency (RF) switch in a silicon-on-insulator (SOI) substrate and methods of manufacture. A method includes forming at least one trench through an insulator layer. The at least one trench is adjacent a device formed in an active region on the insulator layer. The method also includes forming at least one cavity in a substrate under the insulator layer and extending laterally from the at least one trench to underneath the device.Type: GrantFiled: March 15, 2013Date of Patent: May 13, 2014Assignee: International Business Machines CorporationInventors: Alan B. Botula, Dinh Dang, James S. Dunn, Alvin J. Joseph, Peter J. Lindgren
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Patent number: 8674472Abstract: A low harmonic radio-frequency (RF) switch in a silicon-on-insulator (SOI) substrate and methods of manufacture. A method includes forming at least one trench through an insulator layer. The at least one trench is adjacent a device formed in an active region on the insulator layer. The method also includes forming at least one cavity in a substrate under the insulator layer and extending laterally from the at least one trench to underneath the device.Type: GrantFiled: August 10, 2010Date of Patent: March 18, 2014Assignee: International Business Machines CorporationInventors: Alan B. Botula, Dinh Dang, James S. Dunn, Alvin J. Joseph, Peter J. Lindgren
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Patent number: 8674423Abstract: A method of making a semiconductor structure includes forming at least a first trench and a second trench having different depths in a substrate, forming a capacitor in the first trench, and forming a via in the second trench. A semiconductor structure includes a capacitor arranged in a first trench formed in a substrate and a via arranged in a second trench formed in the substrate. The first and second trenches have different depths in the substrate.Type: GrantFiled: November 22, 2011Date of Patent: March 18, 2014Assignee: International Business Machines CorporationInventors: David S. Collins, Kai D. Feng, Zhong-Xiang He, Peter J. Lindgren, Robert M. Rassel
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Patent number: 8645898Abstract: Structures with high-Q value inductors, design structure for high-Q value inductors and methods of fabricating such structures is disclosed herein. A method in a computer-aided design system for generating a functional design model of an inductor is also provided. The method includes: generating a functional representation of a plurality of vertical openings simultaneously formed in a substrate, wherein a first of the plurality of vertical openings is used as through silicon vias and is etched deeper than a second of the plurality of vertical openings used for high-Q inductors; generating a functional representation of a dielectric layer formed in the plurality of vertical openings; and generating a functional representation of a metal layer deposited on the dielectric layer in the plurality of vertical.Type: GrantFiled: June 28, 2012Date of Patent: February 4, 2014Assignee: International Business Machines CorporationInventors: Hanyi Ding, Mete Erturk, Robert A. Groves, Zhong-Xiang He, Peter J. Lindgren, Anthony K. Stamper
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Patent number: 8631570Abstract: Methods of forming through wafer vias (TWVs) and standard contacts in two separate processes to prevent copper first metal layer puddling and shorts are presented. In one embodiment, a method may include forming a TWV into a substrate and a first dielectric layer over the substrate; forming a second dielectric layer over the substrate and the TWV; forming, through the second dielectric layer, at least one contact to the TWV and at least one contact to other structures over the substrate; and forming a first metal wiring layer over the second dielectric layer, the first metal wiring layer contacting at least one of the contacts.Type: GrantFiled: February 9, 2012Date of Patent: January 21, 2014Assignee: International Business Machines CorporationInventors: Peter J. Lindgren, Edmund J. Sprogis, Anthony K. Stamper
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Patent number: 8510329Abstract: The various embodiments of the invention provide a data processing system and method, for applications such as marketing campaign management, speech recognition and signal processing. An exemplary system embodiment includes a first data repository adapted to store a plurality of entity and attribute data; a second data repository adapted to store a plurality of entity linkage data; a metadata data repository adapted to store a plurality of metadata modules, with a first metadata module having a plurality of selectable parameters, received through a control interface, and having a plurality of metadata linkages to a first subset of metadata modules; and a multidimensional data structure. The control interface may modify the plurality of selectable parameters in response to received control information.Type: GrantFiled: May 25, 2005Date of Patent: August 13, 2013Assignee: Experian Marketing Solutions, Inc.Inventors: Nevzat Hurkan Balkir, Marc Louis Gutchell, Peter J. Lindgren, Eric Michael Tagliere
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Patent number: 8445306Abstract: Structures having a hybrid MEMS RF switch and method of fabricating such structures using existing wiring layers of a device is provided. The method of manufacturing a MEMS switch includes forming a forcing electrode from a lower wiring layer of a device and forming a lower electrode from an upper wiring layer of the device. The method further includes forming a flexible cantilever arm over the forcing electrode and the lower electrode such that upon application of a voltage to the forcing electrode, the flexible cantilever arm will contact the lower electrode to close the MEMS switch.Type: GrantFiled: December 24, 2008Date of Patent: May 21, 2013Assignee: International Business Machines CorporationInventors: Peter J. Lindgren, Anthony K. Stamper
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Patent number: 8338265Abstract: A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate. The trench is subsequently filled with a middle-of-line (MOL) dielectric. A contact via may be formed on the trench contact silicide. The trench contact silicide may be formed through a single silicidation reaction with a metal layer or through multiple silicidation reactions with multiple metal layers.Type: GrantFiled: November 12, 2008Date of Patent: December 25, 2012Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Jeffrey B. Johnson, Peter J. Lindgren, Xuefeng Liu, James S. Nakos, Bradley A. Orner, Robert M. Rassel, David C. Sheridan
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Publication number: 20120267794Abstract: Structures with high-Q value inductors, design structure for high-Q value inductors and methods of fabricating such structures is disclosed herein. A method in a computer-aided design system for generating a functional design model of an inductor is also provided. The method includes: generating a functional representation of a plurality of vertical openings simultaneously formed in a substrate, wherein a first of the plurality of vertical openings is used as through silicon vias and is etched deeper than a second of the plurality of vertical openings used for high-Q inductors; generating a functional representation of a dielectric layer formed in the plurality of vertical openings; and generating a functional representation of a metal layer deposited on the dielectric layer in the plurality of vertical.Type: ApplicationFiled: June 28, 2012Publication date: October 25, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hanyi DING, Mete ERTURK, Robert A. GROVES, Zhong-Xiang HE, Peter J. LINDGREN, Anthony K. STAMPER
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Patent number: 8293638Abstract: Method of forming wires in integrated circuits. The methods include forming a wire in a first dielectric layer on a substrate; forming a dielectric barrier layer over the wire and the first dielectric layer; forming a second dielectric layer over the barrier layer; forming one or more patterned photoresist layers over the second dielectric layer; performing a reactive ion etch to etch a trench through the second dielectric layer and not through the barrier layer; performing a second reactive ion etch to extend the trench through the barrier layer; and after performing the second reaction ion etch, removing the one or more patterned photoresist layers, a last formed patterned photoresist layer removed using a reducing plasma or a non-oxidizing plasma. The methods include forming wires by similar methods to a metal-insulator-metal capacitor.Type: GrantFiled: January 20, 2012Date of Patent: October 23, 2012Assignee: International Business Machines CorporationInventors: Jeffrey P. Gambino, Peter J. Lindgren, Anthony K. Stamper
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Patent number: 8236663Abstract: A method and semiconductor device. In the method, at least one partial via is etched in a stacked structure and a border is formed about the at least one partial via. The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer.Type: GrantFiled: September 22, 2009Date of Patent: August 7, 2012Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Keith E. Downes, Peter J Lindgren, Anthony K. Stamper
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Patent number: 8232173Abstract: Structures with high-Q value inductors, design structure for high-Q value inductors and methods of fabricating such structures is disclosed herein. A method in a computer-aided design system for generating a functional design model of an inductor is also provided. The method includes: generating a functional representation of a plurality of vertical openings simultaneously formed in a substrate, wherein a first of the plurality of vertical openings is used as through silicon vias and is etched deeper than a second of the plurality of vertical openings used for high-Q inductors; generating a functional representation of a dielectric layer formed in the plurality of vertical openings; and generating a functional representation of a metal layer deposited on the dielectric layer in the plurality of vertical.Type: GrantFiled: November 1, 2010Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: Hanyi Ding, Mete Erturk, Robert A. Groves, Zhong-Xiang He, Peter J. Lindgren, Anthony K. Stamper
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Patent number: 8234606Abstract: An array of through substrate vias (TSVs) is formed through a semiconductor substrate and a contact-via-level dielectric layer thereupon. A metal-wire-level dielectric layer and a line-level metal wiring structure embedded therein are formed directly on the contact-via-level dielectric layer. The line-level metal wiring structure includes cheesing holes that are filled with isolated portions of the metal-wire-level dielectric layer. In one embodiment, the entirety of the cheesing holes is located outside the area of the array of the TSVs to maximize the contact area between the TSVs and the line-level metal wiring structure. In another embodiment, a set of cheesing holes overlying an entirety of seams in the array of TSVs is formed to prevent trapping of any plating solution in the seams of the TSVs during plating to prevent corrosion of the TSVs at the seams.Type: GrantFiled: April 6, 2011Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: David S. Collins, Alvin Joseph, Peter J. Lindgren, Anthony K. Stamper, Kimball M. Watson