Abstract: In a readout bus architecture having a first column, a readout means is coupled to a photodetector and configured to transfer charge from the photodetector. A select means is coupled to the photodetector and is configured to transfer charge from the photodetector. An address circuit is coupled to the first column through the select means and is configured to generate and decode an address and turn on the select means for the first column if the address matched the first column and if the address circuit received a corrected enable signal indicating that the first column is not defective. A correction circuit is coupled to the address circuit and is configured to generate the corrected enable signal indicating that the first column is not defective if the correction circuit determined that the first column is not defective.

Abstract: A method of manufacturing an imaging subsystem is provided. The method includes manufacturing an image sensing device including a unique identifier. The image sensing device is incorporated into an imaging subsystem. The imaging subsystem is operated and characterization parameters of the image sensing device operation are determined based thereon. The characterization parameters are associated with the unique identifier in a repository of characterization parameters that is separate from the imaging subsystem.

Abstract: An image sensor includes a plurality of pixel sensors arranged in at least one row and a plurality of columns. Each pixel sensor includes a photosensor to generate a photosensor output signal nominally indicative of an intensity of light incident on the photosensor. Each pixel sensor is configured to provide a signal corresponding to the photosensor output signal at an output of the pixel sensor. For each column, a column line couples together the outputs of the pixel sensors belonging to that column and terminates in a column node for that column. Column output circuitry associated with each column provides to image sensor sampling circuitry a signal corresponding to the column node for that column, based on an asserted state of a column enable signal for that column.

Abstract: A method of diagnosing memory and CPU boards by using scan rings which are composed of interconnected shift registers. A maintenance processor (MP) down-loads vector files to the scan rings. The scan rings are transparently partitioned into subsections and each subsection and individual bits are then tagged using a high level language, i.e., a scan path diagnostic language (SPDL). The user of SPDL writes a program in SPDL language addressing a portion of the scan ring. Next, the high level commands are translated into low level machine code and run on the MP. Bits are then loaded into the scan ring and subjected to a test routine. Additional commands are given to correct any errors uncovered and the bits are then reloaded through the MP to the hardware element being tested.