Abstract: A method of diagnosing memory and CPU boards by using scan rings which are composed of interconnected shift registers. A maintenance processor (MP) down-loads vector files to the scan rings. The scan rings are transparently partitioned into subsections and each subsection and individual bits are then tagged using a high level language, i.e., a scan path diagnostic language (SPDL). The user of SPDL writes a program in SPDL language addressing a portion of the scan ring. Next, the high level commands are translated into low level machine code and run on the MP. Bits are then loaded into the scan ring and subjected to a test routine. Additional commands are given to correct any errors uncovered and the bits are then reloaded through the MP to the hardware element being tested.