Abstract: A Serializer/Deserializer (SerDes) is described with an architecture that simultaneously provides flexibility for many different gear ratios as well as reduced power consumption. The SerDes utilizes latches where flops were previously used to help reduce power consumption, among other things. The SerDes also includes a main register bank with a plurality of sub-banks that can be filled according to any number of different schemes, thereby enabling the SerDes to accommodate different output widths.

Abstract: A Serializer/Deserializer (SerDes) is described with an architecture that simultaneously provides flexibility for many different gear ratios as well as reduced power consumption. The SerDes utilizes latches where flops were previously used to help reduce power consumption, among other things. The SerDes also includes a main register bank with a plurality of sub-banks that can be filled according to any number of different schemes, thereby enabling the SerDes to accommodate different output widths.

Abstract: A pipelined receiver comprises a programmable feed forward equalizer (FFE), a programmable decision feedback equalizer (DFE), and logic for controlling a ratio of FFE and DFE to apply to a received signal based on at least one channel parameter.

Abstract: An N-phase clock generation circuit includes an input clock signal comprising a first phase signal, a phase interpolator configured to receive the input clock signal and generate a second phase signal, a first divider element configured to receive the first phase signal and generate an in-phase divided clock signal, a second divider element configured to receive the second phase signal and generate a quadrature divided clock signal, a first delay element configured to receive the in-phase divided clock signal and an in-phase control signal, the first delay element configured to generate a delayed in-phase divided clock signal, an a second delay element configured to receive the quadrature divided clock signal and a quadrature control signal, the second delay element configured to generate a delayed quadrature divided clock signal.

Abstract: A correlation engine includes a first register configured to receive a test data signal, a second register configured to receive a main data signal, first shift logic configured to shift the test data signal by a predetermined value between 0 and 3 symbols, second shift logic configured to shift the main data signal by a predetermined value between 0 and 20 symbols, and comparison logic configured to compare the shifted test data signal and the shifted main data signal to generate an error signal.

Abstract: A serial-to-parallel converter includes a first register bank having first and second register groups, the first register bank configured to receive a communication signal having at least one bit for each unit interval (UI) of a system clock signal, the first register bank having a number of registers corresponding to a number of parallel processing stages, a second register bank having a plurality of register groups, each register group configured to receive the output of at least one of the first and second register groups after a number of unit intervals corresponding to the number of registers in each of the first and second register groups in the first register bank, and a third register bank configured to receive the output of the second register bank after a number of unit intervals corresponding to a number of registers in the second register bank.

Abstract: A clock-data recovery system and method promotes fast adjustment to large phase changes in the incoming data signal. The system can include phase alignment circuitry, clock generator circuitry, time-to-digital converter circuitry, and sampling circuitry. The phase alignment circuitry uses the incoming data signal and a feedback clock signal to generate an output clock signal. The clock generator circuitry uses the output clock signal to generate base phase clock signals of different phases or polarities. The time-to-digital converter circuitry uses the base phase clock signals and the incoming data signal to generate the feedback clock signal. The time-to-digital converter circuitry bases the feedback clock signal on the base phase clock signal that is aligned more closely in phase with the incoming data signal than the other base phase clock signals. The sampling circuitry re-times or recovers the data signal using one or more of the base phase clock signals.

Abstract: A clock-data recovery system and method promotes fast adjustment to large phase changes in the incoming data signal. The system can include phase alignment circuitry, clock generator circuitry, time-to-digital converter circuitry, and sampling circuitry. The phase alignment circuitry uses the incoming data signal and a feedback clock signal to generate an output clock signal. The clock generator circuitry uses the output clock signal to generate base phase clock signals of different phases or polarities. The time-to-digital converter circuitry uses the base phase clock signals and the incoming data signal to generate the feedback clock signal. The time-to-digital converter circuitry bases the feedback clock signal on the base phase clock signal that is aligned more closely in phase with the incoming data signal than the other base phase clock signals. The sampling circuitry re-times or recovers the data signal using one or more of the base phase clock signals.

Abstract: A method for generating mask data includes receiving a set of routing definitions that enable conductor routing schemes having the same cell pitch, identifying locations in response to a characteristic of the set, presenting a representation of a portion of the mask data and applying a select member of the set of routing definitions to locate and size conductors modeled in the mask data. A design tool includes a memory and a processor. The memory stores routing definitions that enable conductor routing schemes having the same cell pitch. The processor receives an input identifying a select routing definition from the set of routing definitions. The processor executes logic that generates an array of points responsive to a characteristic of the routing definitions. The processor further executes logic configured to constrain the relative location and width of conductors in the integrated circuit.

Abstract: A method for generating mask data includes receiving a set of routing definitions that enable conductor routing schemes having the same cell pitch, identifying locations in response to a characteristic of the set, presenting a representation of a portion of the mask data and applying a select member of the set of routing definitions to locate and size conductors modeled in the mask data. A design tool includes a memory and a processor. The memory stores routing definitions that enable conductor routing schemes having the same cell pitch. The processor receives an input identifying a select routing definition from the set of routing definitions. The processor executes logic that generates an array of points responsive to a characteristic of the routing definitions. The processor further executes logic configured to constrain the relative location and width of conductors in the integrated circuit.

Abstract: A method and an apparatus for aligning the phases of clocks of different clock domains of an IC to enable data to be transferred synchronously across the clock domains. The present invention comprises a phase-alignment system that is adjustable via a user interface to enable the clock phases to be adjusted. A user controls the degree of alignment of the phases via the user interface. The present invention enables the phases of clocks of different clock domains to be adjusted even after the IC has been fabricated.

Abstract: A method and an apparatus for aligning the phases of clocks of different clock domains of an IC to enable data to be transferred synchronously across the clock domains. The present invention comprises a phase-alignment system that is adjustable via a user interface to enable the clock phases to be adjusted. A user controls the degree of alignment of the phases via the user interface. The present invention enables the phases of clocks of different clock domains to be adjusted even after the IC has been fabricated.

Abstract: A self calibrating register. In representative embodiments, registers for increasing source synchronous input/output (I/O) data rates by counteracting the inherent systematic sources of system mismatch are disclosed. Systematic sources of system mismatch between bit-line paths and devices, as for example printed circuit board path lengths, package trace lengths, on-chip clock routing, clock skew, device turn-on voltages, etc. are balanced out with respect to a reference clock signal by programmed delays of the data signals. The appropriate delays are obtained via phase shift detection circuitry and are then applied by control circuitry to signal delay circuitry.

Abstract: A self calibrating register. In representative embodiments, registers for increasing source synchronous input/output (I/O) data rates by counteracting the inherent systematic sources of system mismatch are disclosed. Systematic sources of system mismatch between bit-line paths and devices, as for example printed circuit board path lengths, package trace lengths, on-chip clock routing, clock skew, device turn-on voltages, etc. are balanced out with respect to a reference clock signal by programmed delays of the data signals. The appropriate delays are obtained via phase shift detection circuitry and are then applied by control circuitry to signal delay circuitry.

Abstract: An integrated circuit incorporating test access provisions and a system addressable command control register; and provisions for selectably enabling and accessing one or the other for purposes of evaluating integrated circuit functionality.

Abstract: A method and apparatus for low cost set mapping in, for example, a computer graphics processor or communications device efficiently maps elements of one set into another set. When used in conjunction with a graphical display system the low cost set mapping logic enables a memory controller to efficiently communicate with a plurality of memory devices based upon a hierarchical computation scheme. The method and apparatus provide a pseudo-optimal mapping solution. By employing a pseudo-optimal mapping solution the low cost set mapping logic greatly reduces the computational resource required to perform the mapping operation.

Abstract: An improved system and method are provided for generating a design for a regular structure such as a memory array, multiplier array, or adder array embedded in a standard cell control block (SCCB). Once a net list has been generated for the SCCB by a logic synthesis tool, a special class of cells is created for the elements of the regular structure. The net list is modified via a special class mechanism by adding to the cells of the special class one or more special properties that are designed to optimize the placement of the cells of the regular structure. A modified placement and routing tool processes the modified net list by reading and interpreting the special properties so as to generate an improved design for the SCCB.

Abstract: A high voltage tolerant CMOS output driver circuit and high voltage tolerant CMOS input receiver circuit, through the use of shield transistors and the redefinition of the substrate of the PFET devices, is provided. The invention may be incorporated for protection in integrated circuits operating with a lower power supply voltage than externally interfaced devices operating with a higher power supply voltage.

Abstract: The output impedance in a CMOS output driver stage is programmed and compensated by complementary current mirrors that are MOS devices in series with each of the conventional pull-up and pull-down devices. The conduction of these additional complementary devices is controlled according to complementary programming signals that are compensated for variations in manufacturing process parameters as well as for changes in temperature. A P-type programming signal may be referenced to +VDD and be produced from an N-type programming signal referenced to GND by the action of a gate voltage mirror that includes symmetrical N-type and P-type FET's in series. The N-type programming signal may be produced in the first instance from the gate voltage of an N-type FET used in a feedback loop that servos an external programming voltage to track an internally generated reference voltage. That gate voltage exhibits variations that reflect differences attributable to both process variations and to temperature.

Abstract: A CMOS latch circuit having a second feedback inverter and a switching circuit to switch the second feedback inverter out of the circuit when the latch is being loaded. A first circuit implementation uses a single PFET as the switching circuit, and a second circuit implementation incorporates an NFET transistor, in parallel with the PFET. In a third circuit implementation, the switching circuit switches power to and from the second feedback inverter rather than switching the output signal of the inverter to reduce the input capacitance of the latch.