Patents by Inventor Peter J. Mole
Peter J. Mole has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10175272Abstract: A remote differential voltage sensing circuit having a voltage input (Vin) and a voltage output (Vout), comprises a dual differential input stage including a common-source or common-collector differential input stage in parallel with a common-gate or common-base differential input stage. The common-source or collector differential input stage has differential inputs, one coupled to the voltage input (Vin) and the other coupled to the voltage output (Vout). The common-gate or common-base differential input stage has differential inputs, one coupled to a local ground (Agnd) and the other coupled to a remote ground (Rgnd). An output stage is driven by an output of the dual differential input stage and produces an output voltage at the voltage output (Vout). A compensation network is coupled between the voltage output (Vout) and the output of the dual differential input stage.Type: GrantFiled: April 22, 2015Date of Patent: January 8, 2019Assignee: INTERSIL AMERICAS LLCInventors: Wei Chen, Xin Zhang, Gwilym Luff, Peter J. Mole
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Publication number: 20160061866Abstract: A remote differential voltage sensing circuit having a voltage input (Vin) and a voltage output (Vout), comprises a dual differential input stage including a common-source or common-collector differential input stage in parallel with a common-gate or common-base differential input stage. The common-source or collector differential input stage has differential inputs, one coupled to the voltage input (Vin) and the other coupled to the voltage output (Vout). The common-gate or common-base differential input stage has differential inputs, one coupled to a local ground (Agnd) and the other coupled to a remote ground (Rgnd). An output stage is driven by an output of the dual differential input stage and produces an output voltage at the voltage output (Vout). A compensation network is coupled between the voltage output (Vout) and the output of the dual differential input stage.Type: ApplicationFiled: April 22, 2015Publication date: March 3, 2016Applicant: INTERSIL AMERICAS LLCInventors: Wei Chen, Xin Zhang, Gwilym Luff, Peter J. Mole
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Patent number: 8908092Abstract: Methods, systems and devices described herein improve vertical resolution at sides of a four cornered image produced by a scanning projector display device. In accordance with an embodiment, a first plurality of frames (e.g., odd frames) of the image are scanned back and forth from side to side starting at a first line level, in one of the corners. Additionally, a second plurality of frames (e.g., even frames) of the image are scanned back and forth from side to side, starting at a vertical offset level from the first line level, in the same one of the corners. The scanning of the first plurality of frames (e.g., the odd frames) is interleaved with the scanning of the second plurality of frames (e.g., the even frames).Type: GrantFiled: June 28, 2012Date of Patent: December 9, 2014Assignee: Intersil Americas LLCInventors: Morgan Tang, Peter J. Mole, Jayant Vivrekar
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Publication number: 20130235266Abstract: Methods, systems and devices described herein improve vertical resolution at sides of a four cornered image produced by a scanning projector display device. In accordance with an embodiment, a first plurality of frames (e.g., odd frames) of the image are scanned back and forth from side to side starting at a first line level, in one of the corners. Additionally, a second plurality of frames (e.g., even frames) of the image are scanned back and forth from side to side, starting at a vertical offset level from the first line level, in the same one of the corners. The scanning of the first plurality of frames (e.g., the odd frames) is interleaved with the scanning of the second plurality of frames (e.g., the even frames).Type: ApplicationFiled: June 28, 2012Publication date: September 12, 2013Applicant: INTERSIL AMERICAS LLCInventors: Morgan Tang, Peter J. Mole, Jayant Vivrekar
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Patent number: 8450941Abstract: Embodiments of the present invention relate to methods and circuits for use with a system including a light emitting element (e.g., a laser diode or light emitting diode) that is driven by a current produced by a current output digital-to-analog converter (DAC), wherein the light emitting element or the DAC is powered by a supply voltage produced by a voltage supply. In accordance with an embodiment, a measure indicative of a voltage at an output of the DAC is obtained, wherein the voltage at the output of the DAC is indicative of a voltage headroom available for the DAC. The measure indicative of the voltage at the output of the DAC is compared to one or more predetermined references, and the supply voltage is controlled based on the comparison(s).Type: GrantFiled: January 25, 2011Date of Patent: May 28, 2013Assignee: Intersil Americas Inc.Inventors: Dimitrios Katsis, Barry Concklin, Daryl Chamberlin, Peter J. Mole
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Patent number: 8339198Abstract: Provided herein are methods and circuits that reduce a differential capacitance at differential nodes of a differential circuit while boosting the common mode capacitance at the differential nodes, where the differential circuit includes a pair of inputs and differential outputs. A negative capacitance is generated between differential nodes of the differential circuit, which can be accomplished by connecting a negative capacitance circuit between the differential nodes of the differential circuit. In an embodiment, the negative capacitance circuit is connected in parallel with the differential outputs of the differential circuit. In another embodiment, the negative capacitance circuit is connected in parallel with the inputs of the differential circuit. In still another embodiment, the negative capacitance circuit is connected in parallel with the differential internal nodes (i.e., nodes other than the input and output nodes) of the differential circuit.Type: GrantFiled: June 27, 2012Date of Patent: December 25, 2012Assignee: Intersil Americas Inc.Inventors: Peter J. Mole, Philip V. Golden
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Publication number: 20120268206Abstract: Provided herein are methods and circuits that reduce a differential capacitance at differential nodes of a differential circuit while boosting the common mode capacitance at the differential nodes, where the differential circuit includes a pair of inputs and differential outputs. A negative capacitance is generated between differential nodes of the differential circuit, which can be accomplished by connecting a negative capacitance circuit between the differential nodes of the differential circuit. In an embodiment, the negative capacitance circuit is connected in parallel with the differential outputs of the differential circuit. In another embodiment, the negative capacitance circuit is connected in parallel with the inputs of the differential circuit. In still another embodiment, the negative capacitance circuit is connected in parallel with the differential internal nodes (i.e., nodes other than the input and output nodes) of the differential circuit.Type: ApplicationFiled: June 27, 2012Publication date: October 25, 2012Applicant: INTERSIL AMERICAS INC.Inventors: Peter J. Mole, Philip V. Golden
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Patent number: 8228120Abstract: Provided herein are methods and circuits that reduce a differential capacitance at differential nodes of a differential circuit while boosting the common mode capacitance at the differential nodes, where the differential circuit includes a pair of inputs and differential outputs. A negative capacitance is generated between differential nodes of the differential circuit, which can be accomplished by connecting a negative capacitance circuit between the differential nodes of the differential circuit. In an embodiment, the negative capacitance circuit is connected in parallel with the differential outputs of the differential circuit. In another embodiment, the negative capacitance circuit is connected in parallel with the inputs of the differential circuit. In still another embodiment, the negative capacitance circuit is connected in parallel with the differential internal nodes (i.e., nodes other than the input and output nodes) of the differential circuit.Type: GrantFiled: October 23, 2009Date of Patent: July 24, 2012Assignee: Intersil Americas Inc.Inventors: Peter J. Mole, Philip V. Golden
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Publication number: 20120153861Abstract: Embodiments of the present invention relate to methods and circuits for use with a system including a light emitting element (e.g., a laser diode or light emitting diode) that is driven by a current produced by a current output digital-to-analog converter (DAC), wherein the light emitting element or the DAC is powered by a supply voltage produced by a voltage supply. In accordance with an embodiment, a measure indicative of a voltage at an output of the DAC is obtained, wherein the voltage at the output of the DAC is indicative of a voltage headroom available for the DAC. The measure indicative of the voltage at the output of the DAC is compared to one or more predetermined references, and the supply voltage is controlled based on the comparison(s).Type: ApplicationFiled: January 25, 2011Publication date: June 21, 2012Applicant: INTERSIL AMERICAS INC.Inventors: Dimitrios Katsis, Barry Concklin, Daryl Chamberlin, Peter J. Mole
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Patent number: 7863980Abstract: Provided herein are amplifiers including negative capacitance circuits for reducing distortion resulting from a gate-source (or base-emitter) capacitance of output stages of such amplifiers. Such a negative capacitance circuit is connected in parallel with the gate-source (or base-emitter) capacitance of the output stage to shunt the gate-source (or base-emitter) capacitance and thereby reduce distortion. Also provided herein are methods for use with amplifiers including an output stage, including connecting a negative capacitance circuit in parallel with a base-emitter capacitance of the output stage.Type: GrantFiled: May 29, 2009Date of Patent: January 4, 2011Assignee: Intersil Americas Inc.Inventors: Philip V. Golden, Peter J. Mole
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Publication number: 20100301940Abstract: Provided herein are methods and circuits that reduce a differential capacitance at differential nodes of a differential circuit while boosting the common mode capacitance at the differential nodes, where the differential circuit includes a pair of inputs and differential outputs. A negative capacitance is generated between differential nodes of the differential circuit, which can be accomplished by connecting a negative capacitance circuit between the differential nodes of the differential circuit. In an embodiment, the negative capacitance circuit is connected in parallel with the differential outputs of the differential circuit. In another embodiment, the negative capacitance circuit is connected in parallel with the inputs of the differential circuit. In still another embodiment, the negative capacitance circuit is connected in parallel with the differential internal nodes (i.e., nodes other than the input and output nodes) of the differential circuit.Type: ApplicationFiled: October 23, 2009Publication date: December 2, 2010Applicant: Intersil Americas Inc.Inventors: Peter J. Mole, Philip V. Golden
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Patent number: 7609111Abstract: Provided herein are negative capacitance circuits for reducing distortion resulting from a gate-source (or base-emitter) capacitance of an output stage. Such a negative capacitance circuit is connected in parallel with the gate-source (or base-emitter) capacitance of the output stage to shunt the gate-source (or base-emitter) capacitance and thereby reduce distortion.Type: GrantFiled: December 5, 2006Date of Patent: October 27, 2009Assignee: Intersil Americas Inc.Inventors: Philip V. Golden, Peter J. Mole
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Publication number: 20090243720Abstract: Provided herein are amplifiers including negative capacitance circuits for reducing distortion resulting from a gate-source (or base-emitter) capacitance of output stages of such amplifiers. Such a negative capacitance circuit is connected in parallel with the gate-source (or base-emitter) capacitance of the output stage to shunt the gate-source (or base-emitter) capacitance and thereby reduce distortion. Also provided herein are methods for use with amplifiers including an output stage, including connecting a negative capacitance circuit in parallel with a base-emitter capacitance of the output stage.Type: ApplicationFiled: May 29, 2009Publication date: October 1, 2009Applicant: Intersil Americas Inc.Inventors: Philip V. Golden, Peter J. Mole
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Publication number: 20080129424Abstract: Provided herein are negative capacitance circuits for reducing distortion resulting from a gate-source (or base-emitter) capacitance of an output stage. Such a negative capacitance circuit is connected in parallel with the gate-source (or base-emitter) capacitance ofthe output stage to shunt the gate-source (or base-emitter) capacitance and thereby reduce distortion.Type: ApplicationFiled: December 5, 2006Publication date: June 5, 2008Applicant: INTERSIL AMERICAS INC.Inventors: Philip V. Golden, Peter J. Mole
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Patent number: 7053698Abstract: Methods and circuits for extracting a true mean of two signals are provided. A first amplifier input stage (e.g., an n-type stage) is operated when a mean of the two signals approaches an upper rail voltage. A second amplifier input stage (e.g., a p-type stage) is operated when the mean of the two signals approaches a lower rail voltage. A transitioning circuit controls how much each of the first and the second amplifier input stages contributes to an input of a high-gain amplifier output stage, when the mean of the two signal does not approach either of the rail voltages. An output of the high-gain amplifier output stage is fed back to both the first and second amplifier input stages via a feedback stage, which can be a matched buffer stage.Type: GrantFiled: January 24, 2005Date of Patent: May 30, 2006Assignee: Elantec Semiconductor, Inc.Inventor: Peter J. Mole
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Patent number: 6867643Abstract: A rail-to-rail operational amplifier to extract a true mean of two signals. The amplifier includes a first amplifier input stage adapted to operate when a mean of the two signals is near an upper rail voltage. A second amplifier input stage is adapted to operate when the mean of the two signals is near a lower rail voltage. A transitioning circuit is adapted to control how much each of the first and the second amplifier input stages contributes to an input of a high-gain amplifier output stage. An output of the high-gain amplifier output stage is fed back to both the n-type amplifier input stage and the p-type amplifier input stage via a matched buffer stage.Type: GrantFiled: December 11, 2003Date of Patent: March 15, 2005Assignee: Elantec Semiconductor, Inc.Inventor: Peter J. Mole
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Publication number: 20040207449Abstract: A rail-to-rail operational amplifier to extract a true mean of two signals. The amplifier includes a first amplifier input stage adapted to operate when a mean of the two signals is near an upper rail voltage. A second amplifier input stage is adapted to operate when the mean of the two signals is near a lower rail voltage. A transitioning circuit is adapted to control how much each of the first and the second amplifier input stages contributes to an input of a high-gain amplifier output stage. An output of the high-gain amplifier output stage is fed back to both the n-type amplifier input stage and the p-type amplifier input stage via a matched buffer stage.Type: ApplicationFiled: December 11, 2003Publication date: October 21, 2004Applicant: Elantec Semiconductor, Inc.Inventor: Peter J. Mole