Patents by Inventor Peter J. Parbrook

Peter J. Parbrook has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230207730
    Abstract: A semiconductor heterostructure device for use as a component in an optoelectronic component, the device has a substrate, a nanocolumn extending from the substrate, a self-centred passivation layer on top of the nanocolumn, an active region which comprises a quantum well (QW) stack on a vertical side of the nanocolumn and wherein the passivation layer extends horizontally outwards from the nanocolumn to overhang the nanocolumn and the QW stack. The device provides for efficient NC heterostructure based light emitting diodes (LEDs) and other optoelectronic devices with an active region located purely on non-polar facets of the NCs. It also eliminates parasitic current paths allowing core-shell nanorod-based LEDs with emission from the desired facets only.
    Type: Application
    Filed: May 18, 2021
    Publication date: June 29, 2023
    Inventors: Vitaly Z. ZUBIALEVICH, Peter J. PARBROOK, Pietro PAMPILI
  • Patent number: 5585649
    Abstract: A compound semiconductor device with an improved internal current blocking structure. The semiconductor device includes an n-clad layer of II-VI compound semiconductor, a p-clad layer of II-VI compound semiconductor, an active layer of II-VI compound semiconductor between the n-clad and p-clad layers, a very thin current blocking layer of n-type II-VI compound semiconductor on the p-clad layer and providing an opening, a p-contact layer of p-type II-VI compound semiconductor on the p-clad layer and the current blocking layer at the opening, and a p-side electrode on the p-contact layer.
    Type: Grant
    Filed: March 14, 1995
    Date of Patent: December 17, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Ishikawa, Yukie Nishikawa, Masaaki Onomura, Shinji Saito, Peter J. Parbrook, Genichi Hatakoshi
  • Patent number: 5488233
    Abstract: This invention provides a semiconductor light-emitting device including a semiconductor substrate consisting of a compound semiconductor of elements in the third and fifth groups of the period table, a first compound semiconductor layer formed directly on at least a portion of the semiconductor substrate and consisting of a compound semiconductor containing at least In and P, and a second compound semiconductor formed directly on the first compound semiconductor layer and consisting of a compound semiconductor of elements in the second and sixth groups of the periodic table. With this arrangement, it is possible to sufficiently prevent the occurrence of defects in the interface between the semiconductor substrate and the second compound semiconductor layer consisting of the compound semiconductor of the elements in the second and sixth groups of the periodic table.
    Type: Grant
    Filed: March 11, 1994
    Date of Patent: January 30, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Ishikawa, Yukie Nishikawa, Shinji Saito, Peter J. Parbrook, Masaaki Onomura, Koichi Nitta, Genichi Hatakoshi