Abstract: A system for signal processing includes a radio frequency integrated circuit (RFIC) having a plurality of available transmission paths, the RFIC configured to have at least a first communication signal on a first transmission path of the available transmission paths, a plurality of power amplifier/low noise amplifier (PA/LNA) modules selectively connected to the RFIC, each of the PA/LNA modules configured to connect to at least one respective antenna, and switch logic configured to connect the at least first communication signal to any of the plurality of PA/LNA modules prior to power amplification, while preventing the first communication signal from affecting or being affected by another communication signal on another of the plurality of available transmission paths.

Abstract: A system for signal processing includes a radio frequency integrated circuit (RFIC) having a plurality of available transmission paths, the RFIC configured to have at least a first communication signal on a first transmission path of the available transmission paths, a plurality of power amplifier/low noise amplifier (PA/LNA) modules selectively connected to the RFIC, each of the PA/LNA modules configured to connect to at least one respective antenna, and switch logic configured to connect the at least first communication signal to any of the plurality of PA/LNA modules prior to power amplification, while preventing the first communication signal from affecting or being affected by another communication signal on another of the plurality of available transmission paths.

Abstract: Aspects of the disclosure relate to devices, wireless communication apparatuses, methods, and circuitry for a RF power sensor. One aspect is an apparatus including a power sensor transistor configured to receive a radio frequency (RF) input signal and to generate an output indicative of a power of the RF input signal. The apparatus further includes a current source configured to generate a bias current. Also, the apparatus includes a current mirror, which is formed by the power sensor transistor and a second transistor, configured to provide the bias current to the power sensor transistor. The apparatus further includes a feedback circuit, which is coupled to the power sensor transistor and the second transistor, configured to control a drain current of the second transistor with respect to the bias current.

Abstract: Aspects of the disclosure relate to devices, wireless communication apparatuses, methods, and circuitry for a RF power sensor. One aspect is an apparatus including a power sensor transistor configured to receive a radio frequency (RF) input signal and to generate an output indicative of a power of the RF input signal. The apparatus further includes a current source configured to generate a bias current. Also, the apparatus includes a current mirror, which is formed by the power sensor transistor and a second transistor, configured to provide the bias current to the power sensor transistor. The apparatus further includes a feedback circuit, which is coupled to the power sensor transistor and the second transistor, configured to control a drain current of the second transistor with respect to the bias current.

Abstract: Techniques for detecting the type of a media plug inserted into a corresponding jack. In an exemplary embodiment, the output of a first power amplifier for driving a media plug terminal, e.g., the right headphone or left headphone, is selectively coupled to a reference voltage. Measurements of the voltage at a microphone terminal of the media plug may be alternately made for the reference voltage being at a first value and a second value. In an embodiment, the first power amplifier output voltage may be varied by opening or closing a switch. Alternatively, the first power amplifier output voltage may be directly set by an input voltage to the first power amplifier. By detecting changes in the voltages measured at the microphone terminal, it may be determined whether the media plug is of a North American type or European type.

Abstract: Techniques for detecting full insertion of a media plug into a corresponding jack. In an exemplary embodiment, first insertion detection circuitry for detecting the presence of a load is coupled to an innermost terminal of the jack. For North American type audio plugs, the first insertion detection circuitry detects the presence of a left headphone channel coupled to the innermost terminal of the jack. Coupling the insertion detection circuitry to the innermost terminal of the jack advantageously allows detection only when the plug is fully inserted into the jack. Additional detection circuitry may be provided and coupled to the other terminals of the jack. The disclosed techniques may readily be applied to other types of media plugs, e.g., European audio plugs, video plugs, etc.

Abstract: Techniques for sensing the resistance of a load. In an aspect, a sense resistor is provided in series with the load. Each terminal of the sense resistor is alternately coupled via switches to a sense amplifier. A second input of the sense resistor is coupled to a terminal of the load. The voltage drop across the load and the voltage drop across the load plus sense resistor are alternatively measured. These voltage drops may be digitized and used to compute a resistance of the load using, e.g., a digital processor.

Abstract: Techniques for sensing current delivered to a load by a differential output stage, e.g., in a Class D amplifier. In one aspect, voltages across sense resistors coupled in series with first and second branches of the differential output stage are low-passed filtered and digitized. The sense resistors may be coupled in series with the sources of transistors of the first and second branches, wherein the transistors are selectively switchable on and off by input voltage driving voltages. The input driving voltages may correspond to a ternary voltage waveform such that during a given phase, the two transistors coupled in series with the sense resistors may be turned off. Further aspects provide for the first and second branches having cascoded NMOS and/or PMOS transistors, and the sense resistors being provided between a pair of cascoded transistors.

Abstract: Techniques for utilizing a plurality of switches to reduce crosstalk in a headset jack for accommodating both European and North American type headset plugs. In an aspect, a six-switch solution is provided to selectively couple first and second terminals of the jack to a ground and a microphone terminal, and further to selectively couple a ground sensing input to the first or second terminal of the jack. The ground sensing input is provided to left and right audio channel amplifiers for driving the corresponding left and right terminals of the headset, to provide a common-mode reference level to the left and right audio channel amplifiers. In another aspect, at least four physical pins are provided to couple the switches to the ground and microphone terminals of the jack, and the connections between the ground sensing inputs and the jack may be provided adjacent to the jack for better isolation.

Abstract: Techniques for sensing the resistance of a load. In an aspect, a sense resistor is provided in series with the load. Each terminal of the sense resistor is alternately coupled via switches to a sense amplifier. A second input of the sense resistor is coupled to a terminal of the load. The voltage drop across the load and the voltage drop across the load plus sense resistor are alternatively measured. These voltage drops may be digitized and used to compute a resistance of the load using, e.g., a digital processor.

Abstract: A switched-capacitor DC blocking amplifier is disclosed. In an embodiment, an integrated circuit is provided that includes an amplifier having an amplifier input and an amplifier output, a capacitor connected to the amplifier input and configured to receive an input signal, and a switched capacitor circuit coupled to provide a resistance between the amplifier input and the amplifier output. In one implementation, the switched capacitor circuit is configured with a feed forward circuit to reduce aliasing. In another implementation, the switched capacitor circuit includes a switched impedance circuit to reduce noise.

Abstract: Techniques for utilizing a plurality of switches to reduce crosstalk in a headset jack for accommodating both European and North American type headset plugs. In an aspect, a six-switch solution is provided to selectively couple first and second terminals of the jack to a ground and a microphone terminal, and further to selectively couple a ground sensing input to the first or second terminal of the jack. The ground sensing input is provided to left and right audio channel amplifiers for driving the corresponding left and right terminals of the headset, to provide a common-mode reference level to the left and right audio channel amplifiers. In another aspect, at least four physical pins are provided to couple the switches to the ground and microphone terminals of the jack, and the connections between the ground sensing inputs and the jack may be provided adjacent to the jack for better isolation.

Abstract: Techniques for sensing current delivered to a load by a differential output stage, e.g., in a Class D amplifier. In one aspect, voltages across sense resistors coupled in series with first and second branches of the differential output stage are low-passed filtered and digitized. The sense resistors may be coupled in series with the sources of transistors of the first and second branches, wherein the transistors are selectively switchable on and off by input voltage driving voltages. The input driving voltages may correspond to a ternary voltage waveform such that during a given phase, the two transistors coupled in series with the sense resistors may be turned off. Further aspects provide for the first and second branches having cascoded NMOS and/or PMOS transistors, and the sense resistors being provided between a pair of cascoded transistors.

Abstract: Techniques for determining the impedance of a load coupled to an amplifier. In an exemplary embodiment, a mirroring transistor is provided to mirror the current through a transistor of the amplifier output stage to a predetermined ratio. The impedance of the load may be calculated based on the mirrored current and the amplifier output voltage provided to the load. In an exemplary embodiment, the mirrored current may be digitized and provided to a digital load impedance calculation block, which estimates the load impedance based on the digitized current and an indication of the amplifier output voltage. Further techniques are described for calibrating the load impedance calculation scheme, and for differentiating between stereo and mono audio plugs using said techniques.

Abstract: Techniques for detecting full insertion of a media plug into a corresponding jack. In an exemplary embodiment, first insertion detection circuitry for detecting the presence of a load is coupled to an innermost terminal of the jack. For North American type audio plugs, the first insertion detection circuitry detects the presence of a left headphone channel coupled to the innermost terminal of the jack. Coupling the insertion detection circuitry to the innermost terminal of the jack advantageously allows detection only when the plug is fully inserted into the jack. Additional detection circuitry may be provided and coupled to the other terminals of the jack. The disclosed techniques may readily be applied to other types of media plugs, e.g., European audio plugs, video plugs, etc.

Abstract: Techniques for detecting the type of a media plug inserted into a corresponding jack. In an exemplary embodiment, the output of a first power amplifier for driving a media plug terminal, e.g., the right headphone or left headphone, is selectively coupled to a reference voltage. Measurements of the voltage at a microphone terminal of the media plug may be alternately made for the reference voltage being at a first value and a second value. In an embodiment, the first power amplifier output voltage may be varied by opening or closing a switch. Alternatively, the first power amplifier output voltage may be directly set by an input voltage to the first power amplifier. By detecting changes in the voltages measured at the microphone terminal, it may be determined whether the media plug is of a North American type or European type.

Abstract: A switched-capacitor DC blocking amplifier is disclosed. In an embodiment, an integrated circuit is provided that includes an amplifier having an amplifier input and an amplifier output, a capacitor connected to the amplifier input and configured to receive an input signal, and a switched capacitor circuit coupled to provide a resistance between the amplifier input and the amplifier output. In one implementation, the switched capacitor circuit is configured with a feed forward circuit to reduce aliasing. In another implementation, the switched capacitor circuit includes a switched impedance circuit to reduce noise.

Abstract: A radio frequency amplifier with improved linearity and minimal third-order distortion. The amplifier includes a first transistor having first, second and third terminals with the first terminal being an input terminal and the second terminal being the output terminal and the third terminal being a common terminal. A linearization circuit is included having first and second terminals. The first terminal is connected to the common terminal of the transistor and the second terminal is connected to the input terminal of the transistor. In a specific embodiment, the linearization circuit is implemented as a unity gain buffer with an input terminal connected to the common terminal of the transistor and an output terminal connected to the input terminal of the transistor.

Abstract: A radio frequency amplifier with improved linearity and minimal third-order distortion. The amplifier includes a first transistor having first, second and third terminals with the first terminal being an input terminal and the second terminal being the output terminal and the third terminal being a common terminal. A linearization circuit is included having first and second terminals. The first terminal is connected to the common terminal of the transistor and the second terminal is connected to the input terminal of the transistor. In a specific embodiment, the linearization circuit is implemented as a unity gain buffer with an input terminal connected to the common terminal of the transistor and an output terminal connected to the input terminal of the transistor.