Abstract: A method and apparatus for interfacing a serial data signal having an associated data clock signal to a circuit, which is clocked at a slightly higher local clock frequency, employs a D-type flip-flop to sample the data clock signal at the local clock frequency. Another D-type flip-flop stores the sample previous to that stored by the first flip-flop and on the basis of these two stored samples a decision is made as to which clock pulses of the local clock should be passed by a gate to form a modified clock signal. This modified clock signal is used to clock a third flip-flop which reads in the bits of the data signal. The modified clock signal can then be used to clock the data through a shift register so that it can be converted to a parallel format.