Abstract: A digital picture signal processing apparatus has memories each capable of storing digital words representing respective pixels which, when arranged in a two-dimensional array, make up a picture. A read address generator produces a digital read address identifying the position of a set of the stored words to be read from respective different ones of the memories, the words of the set representing a set of pixels so positioned relative to one another as to constitute at least some of the pixels of a portion of the picture. The read address comprises at least one least significant bit (LSB) for each of the coordinate directions. A digital filter has a number of multipliers equal to the number of words in the set and each being connected to a data bus of a respective memory so as to receive a respective one of the set of words read therefrom, and a plurality of coefficient memories.

Abstract: Access to a two-dimensional (2-D) portion of a digital picture signal, the signal being made of a plurality of digital words representing respective pixels (P) when, when arranged in a 2-D array, make up the picture, is achieved as follows. The words are allocated into groups such that the pixels (P) represented by the words of each group make up a 2-D area (T0, T1, etc.) of the picture having a shape and size which is the same for all of the groups, the shape being such that the areas tessellate with one another to constitute at least part of the picture. Each word is stored in one of a plurality of memories (M0 to M15), the number of which is equal to the number of pixels (P) in the 2-D area (T0, T1, etc.), such that, for each pixel position in the area, the words from all of the groups representing the pixels having that pixel position in the area are stored in a respective one of the memories. Then, a set of the stored words which represent a set of pixels are read in parallel.

Abstract: A binary adding apparatus adds together input words (A0-A7, B0-B7) to produce an output word (E0-E7). The apparatus includes a clock signal generator (CK) and adders (FA0-FA7) each connected to receive bits of equal significance of the input words and all having substantially the same propagation delay, the adders being interconnected in cascaded groups (e.g. FA0, FA1), in the order of significance of the bits of the input words, and the number of adders in each group being such that the total propagation delay through each group is less than the clock period. A first set of latches (A1/1-LA1/12) is connected to outputs of the adders (FA0-FA7), the set comprising respective latches (e.g. LA1/1) each connected to receive a sum bit of respective significance and respective latches (e.g. LA1/3) each connected to receive a carry-out bit from a respective one of the groups. An output set of latches (LA3-1-LA3/9) receives the bits of the output word.