Abstract: A multi-processing system (10) comprises a plurality of groups, each having an arbitrary number of processing systems (11, 12). Memory coherency may or may not be established within any particular group. However, each group is intentionally arranged by functionality so that memory coherency, if implemented, only needs to be maintained within the group. Information transfers between two groups are therefore non-coherent by definition. Memory coherency implementation is significantly reduced in the system. A transaction format utilizes group and processing system identifiers to implement the simplified coherency scheme.

Abstract: A method of processing data contained in data packets comprises storing a set of microcode instructions of which some are test instructions prescribing a respective test between a data pattern in a packet and a test pattern; defining by means of bit masks a respective multiplicity of programs each consisting a group of instructions selected from the said set of instructions; providing a particular one of said bit masks; reading out from storage the selected group of instructions in the program defined by said particular one of said bit masks, said selected group including at least one of said test instructions; and executing the instructions in the selected group on data packets. Matches between data patterns in said packets and a test pattern defined by said at least one test instruction may be detected.

Abstract: The present invention provides a highly glycosylated iduronate-2-sulfatase enzyme comprising an iduronate-2-sulfatase polypeptide with at least 5 kilodalton (kDa) more sugar than iduronate-2-sulfatase purified from a natural source, e.g. human liver. The present invention also provides an enzymatically active polypeptide fragment or variant of such a highly glycosylated iduronate-2-sulfatase. The present invention further provides an isolated nucleic acid encoding iduronate-2-sulfatase, as well as an expression vector, a host cell and a method for producing the present highly glycosylated iduronate-2-sulfatase enzyme.

Abstract: A search mechanism improves the performance of a queue system including a queue for storing a plurality of data items and search mechanism by maintaining a key cache data structure having an array of entries, each of which have a key field and a pointer field. The key and pointer fields respectively of each cache entry are used for storing a key value of a different one of the enqueued data items of the queue and a pointer to that enqueued item. The key of each data item to be enqueued is used to generate an index value for accessing a location of the key cache array to obtain immediate access to the corresponding enqueued data item thereby reducing the search time for determining the proper point within the queue for inserting the data item to be added.

Abstract: The present invention provides a highly glycosylated iduronate-2-sulfatase enzyme comprising an iduronate-2-sulfatase polypeptide with at least 5 kilodalton (kDa) more sugar than iduronate-2-sulfatase purified from a natural source, e.g. human liver. The present invention also provides an enzymatically active polypeptide fragment or variant of such a highly glycosylated iduronate-2-sulfatase. The present intention further provides an isolated nucleic acid encoding iduronate-2-sulfatase, as well as an expression vector, a host cell and a method for producing the present highly glycosylated iduronate-2-sulfatase enzyme.

Abstract: The present invention which makes use of knowledge developed at the program writing stage by the programmer or by software tools such as a compiler that some substantial number of data accesses would miss in the cache hierarchy to the detriment of performance and that it would be possible to prefetch the necessary data in parallel with performing useful work. The invention provides a background memory move (BMM) mechanism by which the program can specify such prefetching of data from main memory to a quickly-accessible data cache and by which the program can determine which such prefetches have completed. This mechanism makes it possible to improve the performance of the computer system through the effective use of added concurrency while avoiding the overheads of process-swapping.

Abstract: The present invention provides a highly glycosylated iduronate-2-sulfatase enzyme comprising an iduronate-2-sulfatase polypeptide with at least 5 kilodalton (kDa) more sugar than iduronate-2-sulfatase purified from a natural source, e.g. human liver. The present invention also provides an enzymatically active polypeptide fragment or variant of such a highly glycosylated iduronate-2-sulfatase. The present invention further provides an isolated nucleic acid encoding iduronate-2-sulfatase, as well as an expression vector, a host cell and a method for producing the present highly glycosylated iduronate-2-sulfatase enzyme.

Abstract: The present invention provides a highly glycosylated iduronate-2-sulfatase enzyme comprising an iduronate-2-sulfatase polypeptide with at least 5 kilodalton (kDa) more sugar than iduronate-2-sulfatase purified from a natural source, e.g. human liver. The present invention also provides an enzymatically active polypeptide fragment or variant of such a highly glycosylated iduronate-2-sulfatase. The present invention further provides an isolated nucleic acid encoding iduronate-2-sulfatase, as well as an expression vector, a host cell and a method for producing the present highly glycosylated iduronate-2-sulfatase enzyme.

Abstract: Carboxylic acids produced by carbonylation and having iodide and oxidisable impurities are purified by contacting with hydrogen peroxide and recovering the purified acid by distillation or evaporation. Preferably a strong acid such as sulphuric acid is used as a catalyst. Product contamination by sulphur from sulphuric acid and by excess peroxide may be reduced by the use of metal salts in the recovery step.

Abstract: A secure memory card includes a microprocessor on a single semiconductor chip and one or more non-volatile addressable memory chips. The microprocessor chip and non-volatile memory chips connect in common to an internal card bus for transmitting address, data and control information to such non-volatile memory chips. The microprocessor includes an addressable non-volatile memory for storing information including a number of key values, application specific configuration information and program instruction information. Each chip's memory is organized into a number of blocks or banks and each memory chip is constructed to include security control logic circuits. These circuits include a number of non-volatile and volatile memory devices which are loaded with key and configuration information under the control of the microprocessor only after the microprocessor has determined that the user has successfully performed a predetermined authentication procedure with a host computer.

Abstract: The individual rows of a ROM array are accessed by a row decoder/driver in response to the arrival of the address of the individual row on the address lines. A plurality of programmable switches store the address of a row of ROM array found to contain one or more defects. If the incoming address is that of the defective row each of a plurality of comparators connected to both an address line and the associated switch outputs a coincidence signal to an AND gate. The output of the AND gate accesses a spare row of RAM which thus replaces the defective row of the ROM array. Access to the spare row is automatic upon receipt of the address of the defective row. Each column of the ROM array contains a check bit computed from the remaining contents of the respective column, and the data to be stored in the spare row is generated from the remaining contents of the ROM array. At initialization, the generated data which should have been stored in the defective row is written into the spare row.