Patents by Inventor Peter J. Zievers
Peter J. Zievers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11494322Abstract: A method of operation of a computing system includes: providing a first cluster having a first kernel unit for managing a first reconfigurable hardware device; analyzing an application descriptor associated with an application; generating a first bitstream based on the application descriptor for loading the first reconfigurable hardware device, the first bitstream for implementing at least a first portion of the application; and implementing a first fragment with the first bitstream in the first cluster.Type: GrantFiled: March 8, 2019Date of Patent: November 8, 2022Assignee: Xcelemor, Inc.Inventor: Peter J. Zievers
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Publication number: 20190205271Abstract: A method of operation of a computing system includes: providing a first cluster having a first kernel unit for managing a first reconfigurable hardware device; analyzing an application descriptor associated with an application; generating a first bitstream based on the application descriptor for loading the first reconfigurable hardware device, the first bitstream for implementing at least a first portion of the application; and implementing a first fragment with the first bitstream in the first cluster.Type: ApplicationFiled: March 8, 2019Publication date: July 4, 2019Inventor: Peter J. Zievers
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Patent number: 9495310Abstract: A method of operation of a computing system includes: reconfigurable hardware devices having first application fragment and second application fragment; configuring virtual bus module having virtual bus for electrically coupling the reconfigurable hardware devices; allocating a physical port in the virtual bus, based on availability, for coupling the first application fragment and the second application fragment through the virtual bus; implementing an application through the virtual bus including transferring application data between the first application fragment and the second application fragment; activating a signal buffer interface by the virtual bus module: activating a pin buffer dispatch module for storing the application data from application input buffer, and activating memory request port by roll-back table module, storing the application data, in response to the pin buffer dispatch module; and alerting a roll-back detector including dismissing the application data exceeds a roll-back threshold orType: GrantFiled: May 1, 2015Date of Patent: November 15, 2016Assignee: Xcelemor, Inc.Inventor: Peter J. Zievers
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Patent number: 9152748Abstract: A method of operation of a computing system includes: calculating an initial data connection traversing a center state node of a switching network having an ingress stage, a center stage, and an egress stage; calculating a repacking route across the switching network traversing the center switching node; broadcasting an ingress portion of the repacking route simultaneously to ingress nodes of the ingress stage; broadcasting a center portion of the repacking route simultaneously to center nodes of the center stage with the ingress portion completely deployed; broadcasting an egress portion of the repacking route simultaneously to egress nodes of the egress stage with the center portion completely deployed; and deploying a repacked data connection with the repacking route traversing the center switching node across the switching network synchronously with the initial data connection.Type: GrantFiled: May 4, 2012Date of Patent: October 6, 2015Assignee: Xcelemor, Inc.Inventor: Peter J. Zievers
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Publication number: 20150234755Abstract: A method of operation of a computing system includes: reconfigurable hardware devices having first application fragment and second application fragment; configuring virtual bus module having virtual bus for electrically coupling the reconfigurable hardware devices; allocating a physical port in the virtual bus, based on availability, for coupling the first application fragment and the second application fragment through the virtual bus; implementing an application through the virtual bus including transferring application data between the first application fragment and the second application fragment; activating a signal buffer interface by the virtual bus module: activating a pin buffer dispatch module for storing the application data from application input buffer, and activating memory request port by roll-back table module, storing the application data, in response to the pin buffer dispatch module; and alerting a roll-back detector including dismissing the application data exceeds a roll-back threshold orType: ApplicationFiled: May 1, 2015Publication date: August 20, 2015Applicant: XCELEMOR, INC.Inventor: Peter J. Zievers
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Patent number: 9055070Abstract: A method of operation of a hardware computing system includes: receiving a command stream from a general purpose central processing unit; transferring a command from the command stream by an application manager; activating a programmable execution array, by the application manager, for processing the command; and providing a response through a result stateful multiplexer to the general purpose central processing unit for the command from the command stream.Type: GrantFiled: March 7, 2013Date of Patent: June 9, 2015Assignee: Xcelemor, Inc.Inventor: Peter J. Zievers
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Patent number: 9053266Abstract: A method of operation of a computing system includes: providing reconfigurable hardware devices having a first application fragment and a second application fragment; configuring a virtual bus module having a virtual bus for coupling the reconfigurable hardware devices; allocating a physical port in the virtual bus, based on availability, for communicatively coupling the first application fragment and the second application fragment through the virtual bus; and implementing an application through the virtual bus including transferring application data between the first application fragment and the second application fragment.Type: GrantFiled: May 7, 2012Date of Patent: June 9, 2015Assignee: Xcelemor, Inc.Inventor: Peter J. Zievers
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Patent number: 9055069Abstract: A method of operation of a hardware computing system includes: generating a command stream by a general purpose central processing unit; and receiving, by an application manager, the command stream for executing a command by a programmable execution engine and providing a status through a command execution interface to the general purpose central processing unit for the command from the command stream.Type: GrantFiled: February 11, 2013Date of Patent: June 9, 2015Assignee: Xcelemor, Inc.Inventor: Peter J. Zievers
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Patent number: 8868894Abstract: A method of manufacture of a computing system includes: executing a first application, active and implemented as hardware within a hardware component having of one or more of reconfigurable hardware devices; detecting a trigger event in a first microkernel; generating a first hardware descriptor based on the trigger event, the first hardware descriptor to configure a portion of the hardware component for the first application or a second application; and configuring the portion of the hardware component with the first hardware descriptor while the first application executes concurrently.Type: GrantFiled: May 4, 2012Date of Patent: October 21, 2014Assignee: Xcelemor, Inc.Inventor: Peter J Zievers
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Patent number: 8869087Abstract: A method of operation of an computing system includes: providing a microkernel; controlling a reconfigurable hardware device by the microkernel; configuring an event scoreboard module for monitoring the reconfigurable hardware device; and implementing an application configured in the reconfigurable hardware device including receiving a machine identifier for the reconfigurable hardware device.Type: GrantFiled: May 4, 2012Date of Patent: October 21, 2014Assignee: Xcelemor, Inc.Inventor: Peter J. Zievers
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Patent number: 8756548Abstract: A method for operating a computing system includes: receiving an application-tree for instantiating an application in a reconfigurable hardware device; operating a kernel unit for determining an unoccupied logic-sector within a reconfigurable hardware device; calculating a layout section from the application-tree according to the unoccupied logic-sector for instantiating a fragment circuitry corresponding to the layout section; and determining a system table for connecting the fragment circuitry to other portions of the application to form the application having the fragment circuitry.Type: GrantFiled: May 4, 2012Date of Patent: June 17, 2014Assignee: Xcelemor, Inc.Inventor: Peter J Zievers
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Publication number: 20120284379Abstract: A method of operation of a computing system includes: calculating an initial data connection traversing a center state node of a switching network having an ingress stage, a center stage, and an egress stage; calculating a repacking route across the switching network traversing the center switching node; broadcasting an ingress portion of the repacking route simultaneously to ingress nodes of the ingress stage; broadcasting a center portion of the repacking route simultaneously to center nodes of the center stage with the ingress portion completely deployed; broadcasting an egress portion of the repacking route simultaneously to egress nodes of the egress stage with the center portion completely deployed; and deploying a repacked data connection with the repacking route traversing the center switching node across the switching network synchronously with the initial data connection.Type: ApplicationFiled: May 4, 2012Publication date: November 8, 2012Applicant: XCELEMOR, INC.Inventor: Peter J. Zievers
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Publication number: 20120284492Abstract: A method of manufacture of a computing system includes: executing a first application, active and implemented as hardware within a hardware component having of one or more of reconfigurable hardware devices; detecting a trigger event in a first microkernel; generating a first hardware descriptor based on the trigger event, the first hardware descriptor to configure a portion of the hardware component for the first application or a second application; and configuring the portion of the hardware component with the first hardware descriptor while the first application executes concurrently.Type: ApplicationFiled: May 4, 2012Publication date: November 8, 2012Applicant: XCELEMOR, INC.Inventor: Peter J. Zievers
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Publication number: 20120284439Abstract: A method of operation of a computing system includes: providing reconfigurable hardware devices having a first application fragment and a second application fragment; configuring a virtual bus module having a virtual bus for coupling the reconfigurable hardware devices; allocating a physical port in the virtual bus, based on availability, for communicatively coupling the first application fragment and the second application fragment through the virtual bus; and implementing an application through the virtual bus including transferring application data between the first application fragment and the second application fragment.Type: ApplicationFiled: May 7, 2012Publication date: November 8, 2012Applicant: XCELEMOR, INC.Inventor: Peter J. Zievers
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Publication number: 20120284438Abstract: A method of operation of an computing system includes: providing a microkernel; controlling a reconfigurable hardware device by the microkernel; configuring an event scoreboard module for monitoring the reconfigurable hardware device; and implementing an application configured in the reconfigurable hardware device including receiving a machine identifier for the reconfigurable hardware device.Type: ApplicationFiled: May 4, 2012Publication date: November 8, 2012Applicant: XCELEMOR, INC.Inventor: Peter J. Zievers
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Publication number: 20120284501Abstract: A method of operation of a computing system includes: providing a first cluster having a first kernel unit for managing a first reconfigurable hardware device; analyzing an application descriptor associated with an application; generating a first bitstream based on the application descriptor for loading the first reconfigurable hardware device, the first bitstream for implementing at least a first portion of the application; and implementing a first fragment with the first bitstream in the first cluster.Type: ApplicationFiled: May 4, 2012Publication date: November 8, 2012Applicant: XCELEMOR, INC.Inventor: Peter J. Zievers
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Publication number: 20120284502Abstract: A method for operating a computing system includes: receiving an application-tree for instantiating an application in a reconfigurable hardware device; operating a kernel unit for determining an unoccupied logic-sector within a reconfigurable hardware device; calculating a layout section from the application-tree according to the unoccupied logic-sector for instantiating a fragment circuitry corresponding to the layout section; and determining a system table for connecting the fragment circuitry to other portions of the application to form the application having the fragment circuitry.Type: ApplicationFiled: May 4, 2012Publication date: November 8, 2012Applicant: XCELEMOR, INC.Inventor: Peter J. Zievers
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Patent number: 7162551Abstract: A memory management system adapted to process linked list data files. The system has a plurality of low storage capacity high speed memories and a lower speed high storage capacity bulk memory. An access flow regulator generates requests for the reading and writing of linked list files by the memories. The head and tail buffers and at any intermediate buffers of a linked list are written into the high speed memories. The intermediate buffers are immediately transferred from the high speed memories to said bulk memory while leaving the head buffer and the tail buffer of the linked list in the high speed memories. In read operations, the head and tail buffers are read from the high speed memories. The intermediate buffers are transferred from the bulk memory to said the high speed memory and then read from the high speed memories.Type: GrantFiled: October 31, 2003Date of Patent: January 9, 2007Assignee: Lucent Technologies Inc.Inventor: Peter J. Zievers
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Patent number: 7159049Abstract: A memory management system adapted to process large data files. The system has a plurality of low storage capacity high speed memories and a lower speed high storage capacity bulk memory. An access flow regulator generates requests for the reading and writing of data files by the memories. Large data files have a first part and an excess portion. Both parts of each file are written into the high speed memories. The excess portion of each file is immediately transferred from the high speed memories to the bulk memory while leaving the first part in the high speed memories. In read operations, the first part is read from the high speed memories. The excess portion is transferred from the bulk memory to the high speed memory in a burst mode and then read from the high speed memories.Type: GrantFiled: October 31, 2003Date of Patent: January 2, 2007Assignee: Lucent Technologies Inc.Inventor: Peter J. Zievers
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Patent number: 7120706Abstract: A memory management system for resolving contention for access to a plurality of memories. Signals are continuously applied to an access flow regulator indicating the busy/idle state of each memory. The access flow regulator uses the received signals to determine the present busy/idle state of each of the memories. Requests are applied to the access flow regulator for read and write access to the memories. The access flow regulator operates in response to a determination that one of the memories is currently idle for granting a request access to a memory as soon as it switches from a busy to and idle state.Type: GrantFiled: October 31, 2003Date of Patent: October 10, 2006Assignee: Lucent Technologies Inc.Inventor: Peter J. Zievers