Patents by Inventor Peter Jacob Meier

Peter Jacob Meier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Delay-locked loop and a method of testing a delay-locked loop
    Patent number: 7352165
    Abstract: A delay-locked loop (DLL) of an integrated circuit (IC) with testing circuitry and a method for testing a DLL. During test mode, a phase comparator of the DLL receives a test clock in place of the reference clock and determines the phase difference between the test clock and the clock fed back to the DLL from a clock buffer tree. A variable delay element of the DLL then shifts the reference clock in time by an amount that depends on that phase difference. The variable delay element can be exercised by varying the phase of the test clock with respect to the reference clock by a known phase offset to cause the variable delay element to produce a range of delays. Whether the variable delay element is functioning properly can be determined by checking whether the phase of the test clock is aligned with the phase of the feedback clock.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: April 1, 2008
    Assignee: Avago Technologies General IP Pte Ltd
    Inventors: Alvin Leng Sun Loke, Michael Joseph Gilsdorf, Peter Jacob Meier, Jeffrey R. Rearick
  • Delay-locked loop and a method of testing a delay-locked loop
    Patent number: 7123001
    Abstract: A delay-locked loop (DLL) of an integrated circuit (IC) with testing circuitry and a method for testing a DLL. During test mode, a phase comparator of the DLL receives a test clock in place of the reference clock and determines the phase difference between the test clock and the clock fed back to the DLL from a clock buffer tree. A variable delay element of the DLL then shifts the reference clock in time by an amount that depends on that phase difference. The variable delay element can be exercised by varying the phase of the test clock with respect to the reference clock by a known phase offset to cause the variable delay element to produce a range of delays. Whether the variable delay element is functioning properly can be determined by checking whether the phase of the test clock is aligned with the phase of the feedback clock.
    Type: Grant
    Filed: February 9, 2006
    Date of Patent: October 17, 2006
    Assignee: Avago Tehnologies General IP (Singapore) Pte. Ltd.
    Inventors: Alvin Leng Sun Loke, Michael Joseph Gilsdorf, Peter Jacob Meier, Jeffrey R. Rearick
  • Delay-locked loop and a method of testing a delay-locked loop
    Patent number: 6995554
    Abstract: A delay-locked loop (DLL) of an integrated circuit (IC) with testing circuitry and a method for testing a DLL. During test mode, a phase comparator of the DLL receives a test clock in place of the reference clock and determines the phase difference between the test clock and the dock fed back to the DLL from a clock buffer tree. A variable delay element of the DLL then shifts the reference clock in time by an amount that depends on that phase difference. The variable delay element can be exercised by varying the phase of the test clock with respect to the reference clock by a known phase offset to cause the variable delay element to produce a range of delays. Whether the variable delay element is functioning properly can be determined by checking whether the phase of the test clock is aligned with the phase of the feedback clock.
    Type: Grant
    Filed: June 16, 2004
    Date of Patent: February 7, 2006
    Assignee: Agilent Technologies, Inc.
    Inventors: Alvin Leng Sun Loke, Michael Joseph Gilsdorf, Peter Jacob Meier, Jeffrey R. Rearick