Patents by Inventor Peter James Lindgren
Peter James Lindgren has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8643190Abstract: A microelectronic structure, such as a semiconductor structure, and a method for fabricating the microelectronic structure, include an aperture within a substrate. Into the aperture is located and formed a via. The via may include a through substrate via. The aperture includes, progressing sequentially contiguously at least partially through the substrate: (1) a first comparatively wide region at a surface of the substrate; (2) a constricted region contiguous with the first comparatively wide region; (3) a second comparatively wide region contiguous with the constricted region; and (4) a tapered region contiguous with the second comparatively wide region. The structure of the aperture provides for ease in filling the aperture, as well as void isolation within the via that is filled into the aperture.Type: GrantFiled: November 29, 2010Date of Patent: February 4, 2014Assignee: Ultratech, Inc.Inventors: Edward Crandal Cooney, III, Peter James Lindgren, Doreen Jane Ossenkop, Anthony Kendall Stamper
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Patent number: 8039314Abstract: Back side metal (BSM) delamination induced by chip dicing of silicon wafers is avoided by roughening the polished silicon surface at chip edges by etching. The Thru-Silicon-Via (TSV) structures used in 3D chip integration is masked at the back side from roughening to maintain the polished surface at the TSV structures and, thus, reliable conductivity to the BSM layer.Type: GrantFiled: August 4, 2008Date of Patent: October 18, 2011Assignee: International Business Machines CorporationInventors: Danielle L. DeGraw, Peter James Lindgren, Da-Yuan Shih, Ping-Chuan Wang
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Publication number: 20110129996Abstract: A through substrate via includes an annular conductor layer at a periphery of a through substrate aperture, and a plug layer surrounded by the annular conductor layer. A method for fabricating the through substrate via includes forming a blind aperture within a substrate and successively forming and subsequently planarizing within the blind aperture a conformal conductor layer that does not fill the aperture and plug layer that does fill the aperture. The backside of the substrate may then be planarized to expose at least the planarized conformal conductor layer.Type: ApplicationFiled: February 11, 2011Publication date: June 2, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Peter James Lindgren, Edmund Juris Sprogis, Anthony Kendall Stamper, Kenneth Jay Stein
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Publication number: 20110068477Abstract: A microelectronic structure, such as a semiconductor structure, and a method for fabricating the microelectronic structure, include an aperture within a substrate. Into the aperture is located and formed a via. The via may include a through substrate via. The aperture includes, progressing sequentially contiguously at least partially through the substrate: (1) a first comparatively wide region at a surface of the substrate; (2) a constricted region contiguous with the first comparatively wide region; (3) a second comparatively wide region contiguous with the constricted region; and (4) a tapered region contiguous with the second comparatively wide region. The structure of the aperture provides for ease in filling the aperture, as well as void isolation within the via that is filled into the aperture.Type: ApplicationFiled: November 29, 2010Publication date: March 24, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Edward Crandal Cooney, III, Peter James Lindgren, Doreen Jane Ossenkop, Anthony Kendall Stamper
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Patent number: 7898063Abstract: A through substrate via includes an annular conductor layer at a periphery of a through substrate aperture, and a plug layer surrounded by the annular conductor layer. A method for fabricating the through substrate via includes forming a blind aperture within a substrate and successively forming and subsequently planarizing within the blind aperture a conformal conductor layer that does not fill the aperture and plug layer that does fill the aperture. The backside of the substrate may then be planarized to expose at least the planarized conformal conductor layer.Type: GrantFiled: February 16, 2008Date of Patent: March 1, 2011Assignee: International Business Machines CorporationInventors: Peter James Lindgren, Edmund Juris Sprogis, Anthony Kendall Stamper, Kenneth Jay Stein
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Patent number: 7863180Abstract: A microelectronic structure, such as a semiconductor structure, and a method for fabricating the microelectronic structure, include an aperture within a substrate. Into the aperture is located and formed a via. The via may include a through substrate via. The aperture includes, progressing sequentially contiguously at least partially through the substrate: (1) a first comparatively wide region at a surface of the substrate; (2) a constricted region contiguous with the first comparatively wide region; (3) a second comparatively wide region contiguous with the constricted region; and (4) a tapered region contiguous with the second comparatively wide region. The structure of the aperture provides for ease in filling the aperture, as well as void isolation within the via that is filled into the aperture.Type: GrantFiled: May 6, 2008Date of Patent: January 4, 2011Assignee: International Business Machines CorporationInventors: Edward Crandal Cooney, III, Peter James Lindgren, Dorreen Jane Ossenkop, Anthony Kendall Stamper
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Patent number: 7696586Abstract: A structure. The structure may include a layer of cobalt disilicide that is substantially free of cobalt monosilicide and there is substantially no stringer of an oxide of titanium on the layer of cobalt disilicide. The structure may include a substrate that includes: an insulated-gate field effect transistor (FET) that includes a source, a drain, and a gate; a first layer of cobalt disilicide on the source, said first layer having substantially no cobalt monosilicide, and said first layer having substantially no stringer of an oxide of titanium thereon; a second layer of cobalt disilicide on the drain, said second layer having substantially no cobalt monosilicide having substantially no stringer of an oxide of titanium thereon; and a third layer of cobalt disilicide on the gate, said third layer having substantially no cobalt monosilicide and having substantially no stringer of an oxide of titanium thereon.Type: GrantFiled: July 18, 2008Date of Patent: April 13, 2010Assignee: International Business Machines CorporationInventors: David Paul Agnello, Mary Conroy Bushey, Donna K. Johnson, Jerome Brett Lasky, Peter James Lindgren, Kirk David Peterson
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Publication number: 20100025825Abstract: Back side metal (BSM) delamination induced by chip dicing of silicon wafers is avoided by roughening the polished silicon surface at chip edges by etching. The Thru-Silicon-Via (TSV) structures used in 3D chip integration is masked at the back side from roughening to maintain the polished surface at the TSV structures and, thus, reliable conductivity to the BSM layer.Type: ApplicationFiled: August 4, 2008Publication date: February 4, 2010Inventors: Danielle L. DeGraw, Peter James Lindgren, Da-Yuan Shih, Ping-Chuan Wang
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Publication number: 20090278237Abstract: A microelectronic structure, such as a semiconductor structure, and a method for fabricating the microelectronic structure, include an aperture within a substrate. Into the aperture is located and formed a via. The via may include a through substrate via. The aperture includes, progressing sequentially contiguously at least partially through the substrate: (1) a first comparatively wide region at a surface of the substrate; (2) a constricted region contiguous with the first comparatively wide region; (3) a second comparatively wide region contiguous with the constricted region; and (4) a tapered region contiguous with the second comparatively wide region. The structure of the aperture provides for ease in filling the aperture, as well as void isolation within the via that is filled into the aperture.Type: ApplicationFiled: May 6, 2008Publication date: November 12, 2009Applicant: International Business Machines CorporationInventors: Edward Crandal Cooney, III, Peter James Lindgren, Dorreen Jane Ossenkop, Anthony Kendall Stamper
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Publication number: 20090206488Abstract: A through substrate via includes an annular conductor layer at a periphery of a through substrate aperture, and a plug layer surrounded by the annular conductor layer. A method for fabricating the through substrate via includes forming a blind aperture within a substrate and successively forming and subsequently planarizing within the blind aperture a conformal conductor layer that does not fill the aperture and plug layer that does fill the aperture. The backside of the substrate may then be planarized to expose at least the planarized conformal conductor layer.Type: ApplicationFiled: February 16, 2008Publication date: August 20, 2009Applicant: International Business Machines CorporationInventors: Peter James Lindgren, Edmund Juris Sprogis, Anthony Kendall Stamper, Kenneth Jay Stein
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Publication number: 20080296706Abstract: A structure. The structure may include a layer of cobalt disilicide that is substantially free of cobalt monosilicide and there is substantially no stringer of an oxide of titanium on the layer of cobalt disilicide. The structure may include a substrate that includes: an insulated-gate field effect transistor (FET) that includes a source, a drain, and a gate; a first layer of cobalt disilicide on the source, said first layer having substantially no cobalt monosilicide, and said first layer having substantially no stringer of an oxide of titanium thereon; a second layer of cobalt disilicide on the drain, said second layer having substantially no cobalt monosilicide having substantially no stringer of an oxide of titanium thereon; and a third layer of cobalt disilicide on the gate, said third layer having substantially no cobalt monosilicide and having substantially no stringer of an oxide of titanium thereon.Type: ApplicationFiled: July 18, 2008Publication date: December 4, 2008Inventors: David Paul Agnello, Mary Conroy Bushey, Donna K. Johnson, Jerome Brett Lasky, Peter James Lindgren, Kirk David Peterson
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Patent number: 7411258Abstract: A structure relating to removal of an oxide of titanium generated as a byproduct of a process that forms cobalt disilicide within an insulated-gate field effect transistor (FET). The structure may comprise a layer of cobalt disilicide that is substantially free of cobalt monosilicide, with substantially no stringer of an oxide of titanium on the layer of cobalt disilicide. The structure may alternatively comprise a layer of cobalt disilicide, a patch of an oxide of titanium, and a reagent in contact with the patch at a temperature and for a period of time. The layer is substantially free of cobalt monosilicide. The patch is on the layer of cobalt disilicide. The reagent is adapted to remove the patch within the period of time. The reagent does not chemically react with the layer of cobalt disilicide, and the reagent comprises water, ammonium hydroxide, and hydrogen peroxide.Type: GrantFiled: August 27, 2001Date of Patent: August 12, 2008Assignee: International Business Machines CorporationInventors: David Paul Agnello, Mary Conroy Bushey, Donna K. Johnson, Jerome Brett Lasky, Peter James Lindgren, Kirk David Peterson
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Publication number: 20080174015Abstract: A semiconductor structure and methods for forming the same. A semiconductor fabrication method includes steps of providing a structure. A structure includes (a) a dielectric layer, (b) a first electrically conductive region buried in the dielectric layer, wherein the first electrically conductive region comprises a first electrically conductive material, and (c) a second electrically conductive region buried in the dielectric layer, wherein the second electrically conductive region comprises a second electrically conductive material being different from the first electrically conductive material. The method further includes the steps of creating a first hole and a second hole in the dielectric layer resulting in the first and second electrically conductive regions being exposed to a surrounding ambient through the first and second holes, respectively. Then, the method further includes the steps of introducing a basic solvent to bottom walls and side walls of the first and second holes.Type: ApplicationFiled: January 23, 2007Publication date: July 24, 2008Inventors: Russell Thomas Herrin, Peter James Lindgren, Anthony Kendall Stamper
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Publication number: 20020004303Abstract: A method for removing a formation of oxide of titanium that is generated as a by product of a process that forms cobalt disilicide within an insulated-gate field effect transistor (FET). The method applies a chemical reagent to the FET at a predetermined temperature, and for a predetermined period of time, necessary for removing the formation, wherein the reagent does not chemically react with the cobalt disilicide. A reagent that accomplishes this task comprises water (H2O), ammonium hydroxide (NH4OH), and hydrogen peroxide (H2O2), wherein the NH4OH and the H2O2 each comprise approximately 4% of the total reagent volume. An effective temperature is 65 ° C. combined with a 3 minute period of application.Type: ApplicationFiled: August 27, 2001Publication date: January 10, 2002Inventors: David Paul Agnello, Mary Conroy Bushey, Donna K. Johnson, Jerome Brett Lasky, Peter James Lindgren, Kirk David Peterson
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Patent number: 6335294Abstract: A method for removing a formation of oxide of titanium that is generated as a byproduct of a process that forms cobalt disilicide within an insulated-gate field effect transistor (FET). The method applies a chemical reagent to the FET at a predetermined temperature, and for a predetermined period of time, necessary for removing the formation, wherein the reagent does not chemically react with the cobalt disilicide. A reagent that accomplishes this task comprises water (H2O), ammonium hydroxide (NH4OH), and hydrogen peroxide (H2O2), wherein the NH4OH and the H2O2 each comprise approximately 4% of the total reagent volume. An effective temperature is 65° C. combined with a 3 minute period of application.Type: GrantFiled: April 22, 1999Date of Patent: January 1, 2002Assignee: International Business Machines CorporationInventors: David Paul Agnello, Mary Conroy Bushey, Donna K. Johnson, Jerome Brett Lasky, Peter James Lindgren, Kirk David Peterson