Abstract: A method and system for performing fault tolerant static timing analysis for an electronic network. A composite timing graph is generated by making K+1 copies of the zero-defect timing graph of the network, where K is a predetermined maximum number of defects present on a path of the network, and static timing analysis is performed on the composite timing graph.

Abstract: A method and system for performing fault tolerant static timing analysis for an electronic network. A composite timing graph is generated by making K+1 copies of the zero-defect timing graph of the network, where K is a predetermined maximum number of defects present on a path of the network, and static timing analysis is performed on the composite timing graph.

Abstract: An automated process for timing rule verification for an integrated circuit design is disclosed. The process includes the step of checking the generated timing rules by comparing a given timing rule against a synthesized model to determine timing relationships in the model that are not included in the timing rule and timing relationships in the timing rule that are not present in the model.

Abstract: A method is provided for performing timing correction on a hierarchical integrated circuit design comprising the steps of forming a hierarchical integrated circuit design, applying a hierarchical timing tool to the entire circuit hierarchy, applying a timing correction algorithm to improve timing of the design as measured by the hierarchical timing tool; and applying a parallel timing management tool to multiple applications of the hierarchical timing tool and the timing correction algorithm. Also described is an information handling system including means for implementing the parallel hierarchical timing correction method of the present invention.