Patents by Inventor Peter James Parbrook

Peter James Parbrook has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Light emitter with lowered heterojunction interface barrier
    Patent number: 6005263
    Abstract: A semiconductor device includes a first semiconductor layer formed of first semiconductor, a second semiconductor layer formed on the first semiconductor layer and formed of second semiconductor of a group different from a group to which the first semiconductor belongs, and a third semiconductor layer formed between the first and second semiconductor layers, the third semiconductor layer being one of a layer formed of third semiconductor of the same group as the first semiconductor and having an impurity concentration higher than the first semiconductor layer and a layer formed of fourth semiconductor of the same group as the second semiconductor and having an impurity concentration higher than the second semiconductor layer.
    Type: Grant
    Filed: November 24, 1997
    Date of Patent: December 21, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinji Saito, Masaaki Onomura, Yukie Nishikawa, Masayuki Ishikawa, Peter James Parbrook
  • Semicoductor device having a hetero interface with a lowered barrier
    Patent number: 5821555
    Abstract: A semiconductor device includes a first semiconductor layer formed of first semiconductor, a second semiconductor layer formed on the first semiconductor layer and formed of second semiconductor of a group different from a group to which the first semiconductor belongs, and a third semiconductor layer formed between the first and second semiconductor layers, the third semiconductor layer being one of a layer formed of third semiconductor of the same group as the first semiconductor and having an impurity concentration higher than the first semiconductor layer and a layer formed of fourth semiconductor of the same group as the second semiconductor and having an impurity concentration higher than the second semiconductor layer.
    Type: Grant
    Filed: March 20, 1996
    Date of Patent: October 13, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinji Saito, Masaaki Onomura, Yukie Nishikawa, Masayuki Ishikawa, Peter James Parbrook
  • Light-emitting semiconductor device
    Patent number: 5696389
    Abstract: A light-emitting semiconductor device comprising an n-type cladding layer provided on a surface of a substrate and having concentric first and second parts, a first electrode mounted on the first part of the n-type cladding layer, a p-type cladding layer provided above the surface of the substrate and surrounding the first electrode and the second part of the n-type cladding layer, and a second electrode provided on the p-type cladding layer.
    Type: Grant
    Filed: March 13, 1995
    Date of Patent: December 9, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Ishikawa, Hideto Sugawara, Yukie Nishikawa, Masaaki Onomura, Shinji Saito, Peter James Parbrook, Genichi Hatakoshi, Koichi Nitta, John Rennie, Hiroaki Yoshida, Atsushi Kamata