Patents by Inventor Peter John McElheny
Peter John McElheny has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11784794Abstract: A system may include a host processor, an interposer having memory elements, a coprocessor mounted on the interposer for accelerating tasks received from the host processor, and an auxiliary chip. The coprocessor, interposer, and auxiliary chip may be part of an integrated circuit package. The memory elements on the interposer may convey configuration bit streams to one or more logic sectors in programmable circuitry of the coprocessor. The interposer may be connected to a package substrate of the integrated circuit package using through-silicon vias, such that an active surface of the interposer faces an active surface of the coprocessor. Each logic sector may include one or more data registers that are loaded with configuration data from the memory elements. In some instances, the auxiliary chip may include a secondary memory for storing additional configuration bit streams for configuring the logic sectors of the coprocessor.Type: GrantFiled: August 13, 2020Date of Patent: October 10, 2023Assignee: INTEL CORPORATIONInventors: Peter John McElheny, Aravind Dasu
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Publication number: 20200374102Abstract: A system may include a host processor, an interposer having memory elements, a coprocessor mounted on the interposer for accelerating tasks received from the host processor, and an auxiliary chip. The coprocessor, interposer, and auxiliary chip may be part of an integrated circuit package. The memory elements on the interposer may convey configuration bit streams to one or more logic sectors in programmable circuitry of the coprocessor. The interposer may be connected to a package substrate of the integrated circuit package using through-silicon vias, such that an active surface of the interposer faces an active surface of the coprocessor. Each logic sector may include one or more data registers that are loaded with configuration data from the memory elements. In some instances, the auxiliary chip may include a secondary memory for storing additional configuration bit streams for configuring the logic sectors of the coprocessor.Type: ApplicationFiled: August 13, 2020Publication date: November 26, 2020Applicant: Intel CorporationInventors: Peter John McElheny, Aravind Dasu
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Patent number: 10778414Abstract: A system may include a host processor, an interposer having memory elements, a coprocessor mounted on the interposer for accelerating tasks received from the host processor, and an auxiliary chip. The coprocessor, interposer, and auxiliary chip may be part of an integrated circuit package. The memory elements on the interposer may convey configuration bit streams to one or more logic sectors in programmable circuitry of the coprocessor. The interposer may be connected to a package substrate of the integrated circuit package using through-silicon vias, such that an active surface of the interposer faces an active surface of the coprocessor. Each logic sector may include one or more data registers that are loaded with configuration data from the memory elements. In some instances, the auxiliary chip may include a secondary memory for storing additional configuration bit streams for configuring the logic sectors of the coprocessor.Type: GrantFiled: April 1, 2019Date of Patent: September 15, 2020Assignee: Intel CorporationInventors: Peter John McElheny, Aravind Dasu
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Publication number: 20190229888Abstract: A system may include a host processor, an interposer having memory elements, a coprocessor mounted on the interposer for accelerating tasks received from the host processor, and an auxiliary chip. The coprocessor, interposer, and auxiliary chip may be part of an integrated circuit package. The memory elements on the interposer may convey configuration bit streams to one or more logic sectors in programmable circuitry of the coprocessor. The interposer may be connected to a package substrate of the integrated circuit package using through-silicon vias, such that an active surface of the interposer faces an active surface of the coprocessor. Each logic sector may include one or more data registers that are loaded with configuration data from the memory elements. In some instances, the auxiliary chip may include a secondary memory for storing additional configuration bit streams for configuring the logic sectors of the coprocessor.Type: ApplicationFiled: April 1, 2019Publication date: July 25, 2019Applicant: Intel CorporationInventors: Peter John McElheny, Aravind Dasu
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Patent number: 10291397Abstract: A system may include a host processor, an interposer having memory elements, a coprocessor mounted on the interposer for accelerating tasks received from the host processor, and an auxiliary chip. The coprocessor, interposer, and auxiliary chip may be part of an integrated circuit package. The memory elements on the interposer may convey configuration bit streams to one or more logic sectors in programmable circuitry of the coprocessor. The interposer may be connected to a package substrate of the integrated circuit package using through-silicon vias, such that an active surface of the interposer faces an active surface of the coprocessor. Each logic sector may include one or more data registers that are loaded with configuration data from the memory elements. In some instances, the auxiliary chip may include a secondary memory for storing additional configuration bit streams for configuring the logic sectors of the coprocessor.Type: GrantFiled: December 16, 2016Date of Patent: May 14, 2019Assignee: Intel CorporationInventors: Peter John McElheny, Aravind Dasu
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Publication number: 20180176006Abstract: A system may include a host processor, an interposer having memory elements, a coprocessor mounted on the interposer for accelerating tasks received from the host processor, and an auxiliary chip. The coprocessor, interposer, and auxiliary chip may be part of an integrated circuit package. The memory elements on the interposer may convey configuration bit streams to one or more logic sectors in programmable circuitry of the coprocessor. The interposer may be connected to a package substrate of the integrated circuit package using through-silicon vias, such that an active surface of the interposer faces an active surface of the coprocessor. Each logic sector may include one or more data registers that are loaded with configuration data from the memory elements. In some instances, the auxiliary chip may include a secondary memory for storing additional configuration bit streams for configuring the logic sectors of the coprocessor.Type: ApplicationFiled: December 16, 2016Publication date: June 21, 2018Inventors: Peter John McElheny, Aravind Dasu
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Publication number: 20170365643Abstract: The present invention discloses a memory cell that includes at least two non-volatile resistive memory elements coupled in parallel. The non-volatile resistive memory elements are capable of existing in different resistive states such that each of the different resistive state represents a different data state. The non-volatile resistive memory elements may include multiple layers formed within contact holes.Type: ApplicationFiled: June 17, 2016Publication date: December 21, 2017Inventors: Peter John McElheny, Yue-Song He
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Patent number: 7741716Abstract: Integrated circuit bond pads are provided for forming wire bonds to integrated circuit package pins. Each pad uses a bond pad structure that provides room for under-pad circuitry. The under-pad circuitry can be connected to other circuitry on the integrated circuit, thereby providing efficient use of circuit real estate. The bond pad structures are formed in the dielectric stack portion of the integrated circuit using dummy bond pads and bond pad support structures. Bond pad support structures may be formed from metal in metal interconnect layers. Vias may be used to connect the bond pad support structures to each other and to the dummy bond pads. Bond pad support structures may be formed in a polysilicon layer at the bottom of the dielectric stack. A contact layer contains metal plugs that connect the polysilicon bond pad support structures to the lowermost metal-layer bond pad support structures.Type: GrantFiled: November 8, 2005Date of Patent: June 22, 2010Assignee: Altera CorporationInventors: Girish Venkitachalam, Irfan Rahim, Peter John McElheny
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Patent number: 7514758Abstract: The invention provides a transistor having low leakage currents and methods of fabricating the transistor on a semiconductor substrate. The transistor has a gate and a nonuniform gate oxide under the gate.Type: GrantFiled: June 8, 2005Date of Patent: April 7, 2009Assignee: Altera CorporationInventors: Peter John McElheny, Yowjuang (Bill) Liu
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Patent number: 7235884Abstract: The present invention is a novel method whereby voids or solid opens at the bottom of via can be avoided without drastically altering the resistivity or parasitic capacitances of the whole metal interconnect system. The invention includes in one embodiment a process of forming interconnects and vias in a microelectronic circuit structure. This process includes implanting and/or alloying an impurity element in the local area of the top surface of a metal interconnect at the bottom of a via. Doping may be done before or after formation of the via. After the via is formed, it is filled with a metal such as copper. Another embodiment of the invention is a microelectronic circuit structure manufactured by the aforementioned method.Type: GrantFiled: April 1, 2003Date of Patent: June 26, 2007Assignee: Altera CorporationInventors: Peter John McElheny, Yow-Juang(Bill) W. Liu, Jayakannan Jayapalan, Francois Gregoire
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Patent number: 7107566Abstract: Power consumption on programmable logic devices can be minimized by taking account of gate leakage effects. A logic design system may analyze a logic design to determine which signals are most often high and which signals are low. A logic designer may also provide information on signals to the logic design system. The logic design system may include a gate leakage optimizer and other computer-aided design tools to produce configuration data for programmable logic devices. The programmable logic device may have logic gates formed from stacks of transistors. The configuration data may be used to configure the programmable logic devices so that signals that are usually high are routed to transistors that are high in the stacks, thereby reducing gate leakage and power consumption while maintaining satisfactory performance for the device.Type: GrantFiled: January 22, 2004Date of Patent: September 12, 2006Assignee: Altera CorporationInventor: Peter John McElheny
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Patent number: 6951792Abstract: The invention provides a transistor having low leakage currents and methods of fabricating the transistor on a semiconductor substrate. The transistor has a gate and a nonuniform gate oxide under the gate.Type: GrantFiled: March 11, 2004Date of Patent: October 4, 2005Assignee: Altera CorporationInventors: Peter John McElheny, Yowjuang Bill Liu
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Patent number: 6829127Abstract: A capacitive electrode structure for use in an integrated circuit fabricated on a substrate comprises a first electrode formed by a diffusion region in the substrate, an insulating layer formed on the diffusion region, and a second electrode formed by a conductive layer deposited on said insulating layer. To increase the capacitance per chip area of the capacitive electrode structure, a plurality of recesses are formed in the first electrode on an upper surface thereof with a lower surface of the second electrode substantially following a contour of these recesses. In one embodiment, the capacitive electrode structure is employed for a capacitor formed between a control gate and a floating gate in an EEPROM cell. Capacitors in other types of integrated circuit can be likewise formed using the electrode structure of the present invention.Type: GrantFiled: March 5, 2003Date of Patent: December 7, 2004Assignee: Altera CorporationInventors: Yow-Juang (Bill) Liu, Jayakannan Jayapalan, Francois Gregoire, Peter John McElheny
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Patent number: 6740944Abstract: The invention provides a transistor having low leakage currents and methods of fabricating the transistor on a semiconductor substrate. The transistor has a gate and a nonuniform gate oxide under the gate.Type: GrantFiled: July 3, 2002Date of Patent: May 25, 2004Assignee: Altera CorporationInventors: Peter John McElheny, Yowjuang (Bill) Liu