Patents by Inventor Peter John Mole

Peter John Mole has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10720827
    Abstract: One or more embodiments enable both a fixed bandgap reference voltage and a variable reference voltage to be generated and stored on a capacitor. According to certain aspects, the present embodiments use an additional storage capacitor of smaller size to reduce the sub-threshold leakage of an isolating FET switches at high temperatures. Among other aspects, this enables a more efficient use of chip area for reducing sub-threshold induced leakage than simply increasing the storage capacitor when precision storage is required.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: July 21, 2020
    Assignee: Renesas Electronics America Inc.
    Inventor: Peter John Mole
  • Patent number: 6226509
    Abstract: To reduce the impact of image frequencies generated by mixing an incident carrier signal down to a relatively low intermediate frequency signal used in subsequent signal processing, a mixing frequency is selected such that the generated intermediate frequency signal has a frequency offset relative to DC that is substantially that of a single channel spacing between frequency adjacent incident carrier signals, as shown in FIG. 2. Image rejection is further improved through the integration of a current-driven polyphase filter (36) directly between an input stage (Q1 to Q4) and a mixer stage (Q5 to Q12) of an image reject mixer (FIG. 4) such as to mitigate quadrature divergence between separate in-phase and quadrature paths within the image reject mixer.
    Type: Grant
    Filed: September 15, 1998
    Date of Patent: May 1, 2001
    Assignee: Nortel Networks Limited
    Inventors: Peter John Mole, Henric Van Vliet, Chettan Babla
  • Patent number: 6060956
    Abstract: The invention provides an improved variable capacitance circuit which is substantially linearly controlled using voltage or current control. The circuit comprises two emitter connector transistors and a constant current source or drain forming a current steering circuit. A fixed capacitor is connected to the emitters of the transistors forming a port into the circuit. AC current into the port flows through the fixed capacitor and is fed back through the transistors in a proportion depending on the voltage at their bases. The effective capacitance of the circuit is varied using this variable AC feedback arrangement. Other embodiments use current control to vary the circuit capacitance by varying the effective constant current source level.
    Type: Grant
    Filed: June 19, 1998
    Date of Patent: May 9, 2000
    Assignee: Nortel Networks Corporation
    Inventors: Peter John Mole, Gregory Weng Mun Yuen