Patents by Inventor Peter Joseph Heyrman

Peter Joseph Heyrman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10776143
    Abstract: A technique for assigning physical resources of a data processing system to a virtual machine (VM) includes reading, by a hypervisor executing on the data processing system, a fold factor attribute for the VM. The fold factor attribute defines an anticipated usage of physical resources of the data processing system by the VM. The technique also includes mapping based on a value of the fold factor attribute, by the hypervisor, allocated virtual processors of the VM to the physical resources to maximize processor core access to local memory for ones of the allocated virtual processors that are anticipated to be utilized.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: September 15, 2020
    Assignee: International Business Machines Corporation
    Inventors: Peter Joseph Heyrman, Bret Ronald Olszewski, Sergio Reyes
  • Patent number: 10740127
    Abstract: A technique for assigning physical resources of a data processing system to a virtual machine (VM) includes reading, by a hypervisor executing on the data processing system, a fold factor attribute for the VM. The fold factor attribute defines an anticipated usage of physical resources of the data processing system by the VM. The technique also includes mapping based on a value of the fold factor attribute, by the hypervisor, allocated virtual processors of the VM to the physical resources to maximize processor core access to local memory for ones of the allocated virtual processors that are anticipated to be utilized.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Peter Joseph Heyrman, Bret Ronald Olszewski, Sergio Reyes
  • Publication number: 20150363217
    Abstract: A technique for assigning physical resources of a data processing system to a virtual machine (VM) includes reading, by a hypervisor executing on the data processing system, a fold factor attribute for the VM. The fold factor attribute defines an anticipated usage of physical resources of the data processing system by the VM. The technique also includes mapping based on a value of the fold factor attribute, by the hypervisor, allocated virtual processors of the VM to the physical resources to maximize processor core access to local memory for ones of the allocated virtual processors that are anticipated to be utilized.
    Type: Application
    Filed: June 17, 2014
    Publication date: December 17, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: PETER JOSEPH HEYRMAN, BRET RONALD OLSZEWSKI, SERGIO REYES
  • Publication number: 20150363218
    Abstract: A technique for assigning physical resources of a data processing system to a virtual machine (VM) includes reading, by a hypervisor executing on the data processing system, a fold factor attribute for the VM. The fold factor attribute defines an anticipated usage of physical resources of the data processing system by the VM. The technique also includes mapping based on a value of the fold factor attribute, by the hypervisor, allocated virtual processors of the VM to the physical resources to maximize processor core access to local memory for ones of the allocated virtual processors that are anticipated to be utilized.
    Type: Application
    Filed: September 19, 2014
    Publication date: December 17, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: PETER JOSEPH HEYRMAN, BRET RONALD OLSZEWSKI, SERGIO REYES
  • Patent number: 8468289
    Abstract: A method of dynamically reallocating memory affinity in a virtual machine after migrating the virtual machine from a source computer system to a destination computer system migrates processor states and resources used by the virtual machine from the source computer system to the destination computer system. The method maps memory of the virtual machine to processor nodes of the destination computer system. The method deletes memory mappings in processor hardware, such as translation lookaside buffers and effective-to-real address tables, for the virtual machine on the destination computer system. The method starts the virtual machine on the destination computer system in virtual real memory mode. A hypervisor running on the destination computer system receives a page fault and virtual address of a page for said virtual machine from a processor of the destination computer system and determines if the page is in local memory of the processor.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: June 18, 2013
    Assignee: International Business Machines Corporation
    Inventors: David Alan Hepkin, Peter Joseph Heyrman, Bret Ronald Olszewski
  • Patent number: 8407515
    Abstract: A method and apparatus for transparently handling recurring correctable errors and uncorrectable errors in a mirrored memory system prevents costly system shutdowns for correctable memory errors or system failures from uncorrectable memory errors. When a high number of correctable errors are detected for a given memory location, a memory relocation mechanism in the hypervisor moves the data associated with the memory location to an alternate physical memory location transparently to the partition such that the partition has no knowledge that the physical memory actualizing the memory location has been changed. When a correctable error occurs, the memory relocation mechanism uses data from a partner mirrored memory block as a data source for the memory block with the uncorrectable error and then relocates the data to a newly allocated memory block to replace the memory block with the uncorrectable error.
    Type: Grant
    Filed: May 6, 2008
    Date of Patent: March 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Peter Joseph Heyrman, Naresh Nayar, Gary Ross Ricard
  • Patent number: 8255639
    Abstract: A method and apparatus for transparently handling recurring correctable errors to prevent costly system shutdowns for correctable memory errors or system failures from uncorrectable memory errors. When a high number of correctable errors are detected for a given memory location, the hypervisor moves the data associated with the memory location to an alternate physical memory location transparently to the partition such that the partition has no knowledge that the physical memory actualizing the memory location has been changed. Similarly, the hypervisor can move direct memory access (DMA) memory locations using an I/O translation table.
    Type: Grant
    Filed: May 6, 2008
    Date of Patent: August 28, 2012
    Assignee: International Business Machines Corporation
    Inventors: Peter Joseph Heyrman, Naresh Nayar, Gary Ross Ricard
  • Patent number: 8234645
    Abstract: An apparatus, program product and method support the deallocation of a data structure in a multithreaded computer without requiring the use of computationally expensive semaphores or spin locks. Specifically, access to a data structure is governed by a shared pointer that, when a request is received to deallocate the data structure, is initially set to a value that indicates to any thread that later accesses the pointer that the data structure is not available. In addition, to address any thread that already holds a copy of the shared pointer, and thus is capable of accessing the data structure via the shared pointer after the initiation of the request, all such threads are monitored to determine whether any thread is still using the shared pointer by determining whether any thread is executing program code that is capable of using the shared pointer to access the data structure.
    Type: Grant
    Filed: January 8, 2008
    Date of Patent: July 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: William Joseph Armstrong, Peter Joseph Heyrman, Naresh Nayar
  • Patent number: 8209692
    Abstract: An apparatus, program product and method support the deallocation of a data structure in a multithreaded computer without requiring the use of computationally expensive semaphores or spin locks. Specifically, access to a data structure is governed by a shared pointer that, when a request is received to deallocate the data structure, is initially set to a value that indicates to any thread that later accesses the pointer that the data structure is not available. In addition, to address any thread that already holds a copy of the shared pointer, and thus is capable of accessing the data structure via the shared pointer after the initiation of the request, all such threads are monitored to determine whether any thread is still using the shared pointer by determining whether any thread is executing program code that is capable of using the shared pointer to access the data structure.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: June 26, 2012
    Assignee: International Business Machines Corporation
    Inventors: William Joseph Armstrong, Peter Joseph Heyrman, Naresh Nayar
  • Patent number: 8024728
    Abstract: A computer implemented method, data processing system, and computer usable program code are provided for dispatching virtual processors. A determination is made as to whether a physical processor in a set of physical processors is idle, and, if so, a determination is made as to whether an affinity map for the idle physical processor exists. Responsive to an existence of the affinity map, a determination is made as to whether a virtual processor last mapped to the idle physical processor is ready to run using the affinity map and a dispatch algorithm. Responsive to identifying a ready-to-run virtual processor whose affinity map indicates that the idle physical processor is mapped to this virtual processor in its preceding dispatch, the ready-to-run virtual processor is dispatched to the idle physical processor. Thus, memory affinity is maintained between physical and virtual processors when the memory affinity is not expired.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: September 20, 2011
    Assignee: International Business Machines Corporation
    Inventors: Vaijayanthimala K. Anand, Peter Joseph Heyrman, Bret R. Olszewski
  • Publication number: 20090282300
    Abstract: A method and apparatus for transparently handling recurring correctable errors and uncorrectable errors in a mirrored memory system prevents costly system shutdowns for correctable memory errors or system failures from uncorrectable memory errors. When a high number of correctable errors are detected for a given memory location, a memory relocation mechanism in the hypervisor moves the data associated with the memory location to an alternate physical memory location transparently to the partition such that the partition has no knowledge that the physical memory actualizing the memory location has been changed. When a correctable error occurs, the memory relocation mechanism uses data from a partner mirrored memory block as a data source for the memory block with the uncorrectable error and then relocates the data to a newly allocated memory block to replace the memory block with the uncorrectable error.
    Type: Application
    Filed: May 6, 2008
    Publication date: November 12, 2009
    Inventors: Peter Joseph Heyrman, Naresh Nayar, Gary Ross Ricard
  • Publication number: 20090282210
    Abstract: A method and apparatus for transparently handling recurring correctable errors to prevent costly system shutdowns for correctable memory errors or system failures from uncorrectable memory errors. When a high number of correctable errors are detected for a given memory location, the hypervisor moves the data associated with the memory location to an alternate physical memory location transparently to the partition such that the partition has no knowledge that the physical memory actualizing the memory location has been changed. Similarly, the hypervisor can move direct memory access (DMA) memory locations using an I/O translation table.
    Type: Application
    Filed: May 6, 2008
    Publication date: November 12, 2009
    Inventors: Peter Joseph Heyrman, Naresh Nayar, Gary Ross Ricard
  • Publication number: 20080163203
    Abstract: A computer implemented method, data processing system, and computer usable program code are provided for dispatching virtual processors. A determination is made as to whether a physical processor in a set of physical processors is idle, and, if so, a determination is made as to whether an affinity map for the idle physical processor exists. Responsive to an existence of the affinity map, a determination is made as to whether a virtual processor last mapped to the idle physical processor is ready to run using the affinity map and a dispatch algorithm. Responsive to identifying a ready-to-run virtual processor whose affinity map indicates that the idle physical processor is mapped to this virtual processor in its preceding dispatch, the ready-to-run virtual processor is dispatched to the idle physical processor. Thus, memory affinity is maintained between physical and virtual processors when the memory affinity is not expired.
    Type: Application
    Filed: December 28, 2006
    Publication date: July 3, 2008
    Inventors: Vaijayanthimala K. Anand, Peter Joseph Heyrman, Bret R. Olszewski
  • Publication number: 20080134188
    Abstract: An apparatus, program product and method support the deallocation of a data structure in a multithreaded computer without requiring the use of computationally expensive semaphores or spin locks. Specifically, access to a data structure is governed by a shared pointer that, when a request is received to deallocate the data structure, is initially set to a value that indicates to any thread that later accesses the pointer that the data structure is not available. In addition, to address any thread that already holds a copy of the shared pointer, and thus is capable of accessing the data structure via the shared pointer after the initiation of the request, all such threads are monitored to determine whether any thread is still using the shared pointer by determining whether any thread is executing program code that is capable of using the shared pointer to access the data structure.
    Type: Application
    Filed: January 8, 2008
    Publication date: June 5, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: William Joseph Armstrong, Peter Joseph Heyrman, Naresh Nayar
  • Patent number: 7328438
    Abstract: An apparatus, program product and method support the deallocation of a data structure in a multithreaded computer without requiring the use of computationally expensive semaphores or spin locks. Specifically, access to a data structure is governed by a shared pointer that, when a request is received to deallocate the data structure, is initially set to a value that indicates to any thread that later accesses the pointer that the data structure is not available. In addition, to address any thread that already holds a copy of the shared pointer, and thus is capable of accessing the data structure via the shared pointer after the initiation of the request, all such threads are monitored to determine whether any thread is still using the shared pointer by determining whether any thread is executing program code that is capable of using the shared pointer to access the data structure.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: February 5, 2008
    Assignee: International Business Machines Corporation
    Inventors: Willaim Joseph Armstrong, Peter Joseph Heyrman, Naresh Nayar
  • Patent number: 7222343
    Abstract: An apparatus, program product and method dynamically assign threads to computer resources in a multithreaded computer including a plurality of physical subsystems based upon specific “types” associated with such threads. In particular, thread types are allocated resources that are resident within the same physical subsystem in a computer, such that newly created threads and/or reactivated threads of those particular thread types are dynamically assigned to the resources allocated to their respective thread types. As such, those threads sharing the same type are generally assigned to computer resources that are resident within the same physical subsystem of a computer, which often reduces cross traffic between multiple physical subsystems resident in a computer, and thus improves overall system performance.
    Type: Grant
    Filed: January 16, 2003
    Date of Patent: May 22, 2007
    Assignee: International Business Machines Corporation
    Inventors: Peter Joseph Heyrman, Karl Robert Huppler, Henry Joseph May, Kenneth Charles Vossen
  • Publication number: 20040194096
    Abstract: An apparatus, program product and method support the deallocation of a data structure in a multithreaded computer without requiring the use of computationally expensive semaphores or spin locks. Specifically, access to a data structure is governed by a shared pointer that, when a request is received to deallocate the data structure, is initially set to a value that indicates to any thread that later accesses the pointer that the data structure is not available. In addition, to address any thread that already holds a copy of the shared pointer, and thus is capable of accessing the data structure via the shared pointer after the initiation of the request, all such threads are monitored to determine whether any thread is still using the shared pointer by determining whether any thread is executing program code that is capable of using the shared pointer to access the data structure.
    Type: Application
    Filed: March 27, 2003
    Publication date: September 30, 2004
    Applicant: International Business Machines Corporation
    Inventors: William Joseph Armstrong, Peter Joseph Heyrman, Naresh Nayar
  • Publication number: 20040143833
    Abstract: An apparatus, program product and method dynamically assign threads to computer resources in a multithreaded computer including a plurality of physical subsystems based upon specific “types” associated with such threads. In particular, thread types are allocated resources that are resident within the same physical subsystem in a computer, such that newly created threads and/or reactivated threads of those particular thread types are dynamically assigned to the resources allocated to their respective thread types. As such, those threads sharing the same type are generally assigned to computer resources that are resident within the same physical subsystem of a computer, which often reduces cross traffic between multiple physical subsystems resident in a computer, and thus improves overall system performance.
    Type: Application
    Filed: January 16, 2003
    Publication date: July 22, 2004
    Applicant: International Business Machines Corporation
    Inventors: Peter Joseph Heyrman, Karl Robert Huppler, Henry Joseph May, Kenneth Charles Vossen