Patents by Inventor Peter K. Charvat

Peter K. Charvat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5874358
    Abstract: A novel high performance and reliable interconnection structure for preventing via delamination. The interconnection structure of the present invention comprises a via connection which extends into and undercuts an underlying interconnection line to lock the via connection into the interconnection line.
    Type: Grant
    Filed: February 25, 1997
    Date of Patent: February 23, 1999
    Assignee: Intel Corporation
    Inventors: Alan M. Myers, Peter K. Charvat, Thomas A. Letson, Shi-ning Yang, Peng Bai
  • Patent number: 5619071
    Abstract: A novel high performance and reliable interconnection structure for preventing via delamination. The interconnection structure of the present invention comprises a via connection which extends into and undercuts an underlying interconnection line to lock the via connection into the interconnection line.
    Type: Grant
    Filed: August 15, 1995
    Date of Patent: April 8, 1997
    Assignee: Intel Corporation
    Inventors: Alan M. Myers, Peter K. Charvat, Thomas A. Letson, Shi-ning Yang, Peng Bai
  • Patent number: 5549784
    Abstract: The present invention discloses a method for the etching of insulating films, specifically silicon oxide films, using a fluorine-helium-oxygen gas mixture in the fabrication of semiconductor devices. The method utilizes a prior art reactive ion etch system and adds a quantity of helium to a pre-established fluorine-oxygen chemistry to reactively etch the silicon oxide film while minimizing the occurrence of gate charging resulting from damage to the gate oxide. The addition of helium gas into the etch chemistry must be such that the flow of helium is at least 20% of the sum of the total fluorine, helium, and oxygen flows. The resulting etch chemistry, which can be used in any commercially available reactive ion etch system, produces a more uniform etch while reducing gate oxide damage so as to minimize charging of the semiconductor gate.
    Type: Grant
    Filed: September 14, 1994
    Date of Patent: August 27, 1996
    Assignee: Intel Corporation
    Inventors: Kevin F. Carmody, Peter K. Charvat, Gilroy J. Vandentop
  • Patent number: 5470790
    Abstract: A novel high performance and reliable interconnection structure for preventing via delamination. The interconnection structure of the present invention comprises a via connection which extends into and undercuts an underlying interconnection line to lock the via connection into the interconnection line.
    Type: Grant
    Filed: October 17, 1994
    Date of Patent: November 28, 1995
    Assignee: Intel Corporation
    Inventors: Alan M. Myers, Peter K. Charvat, Thomas A. Letson, Shi-ning Yang, Peng Bai
  • Patent number: 5262279
    Abstract: A dry process for stripping photoresist from a polyimide surface formed on a substrate is described. The present invention is practiced after a polyimide layer has been etched. Prior to etching, the polyimide surface is masked with photoresist which is then patterned. The polyimide is etched in exposed regions, for example to form vias to expose contacts located beneath the polyimide layer. The present invention then strips the photoresist in a single wafer downstream plasma etcher in a plasma comprising oxygen radicals. The polyimide is subjected to a short preheat before introduction of the oxygen plasma, and is also heated during the stripping process. The strip proceeds until an endpoint is detected. The endpoint is detected by a change in the spectral emission of the plasma which occurs due to a decrease in the amount of CH.sub.3 radicals present in the system when the polyimide surface is reached. A short timed over-etch is then employed to ensure complete removal of the photoresist.
    Type: Grant
    Filed: September 9, 1992
    Date of Patent: November 16, 1993
    Assignee: Intel Corporation
    Inventors: Chi-Hwa Tsang, Peter K. Charvat, Robert M. Guptill
  • Patent number: 5242864
    Abstract: A process for forming a protective polyimide layer over a semiconductor substrate includes the steps of curing a deposited polyamic acid layer at a temperature which is sufficient to reduce the etch rate of the acid layer when subsequently exposed to a developer. After formation of a photoresist masking layer over the polyamic acid, the substrate is exposed to a developer to define a plurality of bonding pad openings therein. The developer permeates into the acid layer to form a salt in the regions beneath the openings. Subsequent hardbaking imidizes the polyamic acid, but not the salt regions. Removing the photoresist layer also develops the polyimide which removes the salt regions to expose the underlying bonding pads.
    Type: Grant
    Filed: June 5, 1992
    Date of Patent: September 7, 1993
    Assignee: Intel Corporation
    Inventors: Maxine Fassberg, Melton C. Bost, Krishnamurthy Murali, Peter K. Charvat, Lynn A. Price, Robert C. Lindstedt
  • Patent number: 5202291
    Abstract: An anisotropic reactive ion etching of an aluminum metal film of a semiconductor device. The device is placed in a reactive ion etcher using a CF.sub.4, Cl.sub.2 and BCl.sub.3 gas mixture to anisotropically etch the aluminum metal film layer wherein the gas mixture has a ratio of CF.sub.4 :Cl.sub.2 such that the aluminum etch rate increases as the amount of CF.sub.4 relative to Cl.sub.2 increases.
    Type: Grant
    Filed: May 8, 1992
    Date of Patent: April 13, 1993
    Assignee: Intel Corporation
    Inventors: Peter K. Charvat, Chris Kardas