Abstract: A method and apparatus for preempting an operation in a nonvolatile writeable memory is performed using a pin. Preempting an operation is accomplished by either suspending the operation or by aborting the operation. Once an operation is suspended in the nonvolatile writeable memory, other operations can then be performed. Subsequently the suspended operation may be resumed.

Abstract: A processor-implemented method is described for updating a datum stored in a nonvolatile memory, bits of which cannot be overwritten from a first logical state to a second logical state without a prior erasure. A first storage location in the memory that stores a first version of the datum is accessed. A status field of the first storage location is checked to determine whether the first version of the datum has been superseded. If the status field of the first storage location indicates that the first version of the datum has not been superseded, then a most recent version of the datum is stored in a second storage location of the memory. An address of the second storage location is then written into a next location address field of the first storage location and the status field of the first storage location is written to indicate that the first version of the datum has been superseded such that the datum is updated without the prior erasure of the memory.

Abstract: A method and apparatus for controlling use of an electronic system is described. Use of the electronic system is controlled by programming at least one unique code into an auxiliary memory of the electronic system. The auxiliary memory is a permanently lockable memory that is located outside of a main memory array space. The unique code is compared to at least one component code. Use of the electronic system is controlled based on a predefined relationship between the unique code and the component code.

Abstract: A method and apparatus for preempting an operation in a nonvolatile writeable memory is performed using a pin. Preempting an operation is accomplished by either suspending the operation or by aborting the operation. Once an operation is suspended in the nonvolatile writeable memory, other operations can then be performed. Subsequently the suspended operation may be resumed.

Abstract: An interface for a read-while-write memory. A memory device includes a single-chip memory array and an interface that is responsive to one or more commands to configure the memory array in a read-while-write configuration.

Abstract: A programmable logic device that includes a voltage input and a detection circuit coupled to the voltage input is described. The detection circuit detects whether a voltage applied to the voltage input exceeds a predetermined value. The programmable logic device also includes a configuration circuit coupled to the detection circuit. The configuration circuit configures the programmable logic device to receive a current sufficient for program and erase operations through the voltage input in response to the detection circuit detecting that the voltage exceeds the predetermined value.

Abstract: A method and apparatus suspend a program operation in a nonvolatile writeable memory. The nonvolatile writeable memory includes a memory array, a command register and memory array control circuitry. The command register decodes a program suspend command and provides a suspend signal as an output. The memory array control circuitry is coupled to receive the suspend signal from the command register. The memory array control circuitry performs a program operation in which data is written to the memory array. The memory array control circuitry suspends the program operation upon receiving the suspend signal.

Abstract: A method and apparatus for partitioning a flash memory device is provided. The flash memory device includes a plurality of partitions, each partition able to be read, written, or erased simultaneously with the other partitions.

Abstract: A method and apparatus suspend operations in a flash memory in order to read code from the flash memory. A system comprises a processor and a nonvolatile writeable memory coupled together. A non-read operation is preempted in the nonvolatile writeable memory responsive to an input at a pin of the nonvolatile writeable memory. The preemption occurs by either suspending the non-read operation or aborting the non-read operation. Code is read from the nonvolatile writeable memory and provided to the processor. Subsequently, the non-read operation is resumed at where it was suspended, or is started anew.

Abstract: A method and apparatus suspend a program operation in a nonvolatile writeable memory. The nonvolatile writeable memory includes a memory array, a command register, and memory array control circuitry. The command register decodes a program suspend command and provides a suspend signal as an output. The memory array control circuitry is coupled to receive the suspend signal from the command register. The memory array control circuitry performs a program operation in which data is written to the memory array. The memory array control circuitry suspends the program operation upon receiving the suspend signal.

Abstract: A nonvolatile memory includes a memory array and a control circuit having a command latch and a command decoder. The control circuit receives an output enable signal and a write enable signal to control memory operations of the memory array in accordance with a command latched into the command latch via the command decoder. A write protection circuit is also provided that disables the command latch and the command decoder when the output and write enable signals are both active. The protection circuit includes a pulse generator that generates a reset signal to reset the command latch to the read array state and a control logic that causes the pulse generator to assert the reset signal when an output enable signal and a write enable signal of the memory are both active until after the write enable signal has been forced internally inactive and the command latch closed.

Abstract: A method and apparatus for protecting data stored in a nonvolatile memory. First, a locking signal is initiated to indicate to the memory that write and erase operations are to be prevented. Next, in response to this locking signal, the supply voltage that supports write and erase operations in the memory is lowered below a threshold value. In doing so, protection circuitry that is contained within the memory prevents write and erase operations in the memory.

Abstract: A nonvolatile memory includes a memory array, control circuitry coupled to the memory array for controlling memory operations with respect to the memory array, and a configuration cell coupled to the control circuitry for generating a configuration signal to configure the nonvolatile memory with respect to the memory operations. The configuration cell can be programmed in a first state and a second state. A configuration logic is coupled to the configuration cell and the control circuitry for altering the configuration signal from the configuration cell to the control circuitry without causing the configuration cell to be reprogrammed. The configuration logic includes an exclusive or gate that temporarily alters the configuration signal without affecting a programmed state of the configuration cell.

Abstract: A nonvolatile memory and a method for controlling the nonvolatile memory to switch between first and second data widths are described. The nonvolatile memory includes a first memory array, a second memory array, a first plurality of data pads, and a second plurality of data pads. A data width control circuit selectively couples the first and second plurality of data pads to the first and second memory arrays. A data width configuration cell is provided for configuring data width of the nonvolatile memory. A data width select circuit controls the data width control circuit to selectively couple the first and second plurality of data pads to the first and second memory arrays under the control of the data width configuration cell. When the data width configuration cell is in a first state, the first and second memory arrays are coupled to the first and second plurality of data pads such that the nonvolatile memory has a first data width.

Abstract: A circuit for accessing data which may be stored in a flash EEPROM memory array in sixteen bit quantities has apparatus for writing data to the array in eight bit quantities which quantities may be either the lower or upper byte of a word and appear at identical input terminals, apparatus for writing data to the array in sixteen bit quantities, apparatus for reading data from the array to identical output terminals in eight bit quantities which quantities may be either the lower or upper byte of a word, and apparatus for reading data from the array in sixteen bit quantities. The circuit also has apparatus for reading data from the array in eight and sixteen bit quantities during periods in which an erase operation conducted on sixteen bits is suspended.

Abstract: A nonvolatile memory includes a first block and a second block. The first block comprises a first memory cell and a first source line coupled to a source of the first memory cell. The second block comprises a second memory cell and a second source line coupled to a source of the second memory cell. A first source switch is coupled to the first source line for selectively coupling a first potential, a second potential, and a third potential to the first source line. The second potential has a voltage intermediate between the first potential and the third potential. A second source switch is coupled to the second source line for selectively coupling one of the first, second, and third potentials to the second source line. A block select circuit receives a block address for selecting one of the first and second source switches to couple one of the first, second, and third potentials to its respective one of the first and second source lines.

Abstract: A nonvolatile memory device residing on a substrate is described. The memory device includes a first block and a second block. The first block includes a first sub-block comprising a first memory cell, a first bit line coupled to a drain of the first memory cell, and a first source line coupled to a source of the first memory cell. The first block also includes a second sub-block which includes a second memory cell, a second bit line coupled to a drain of the second memory cell, and a second source line coupled to a source of the second memory cell. The second block comprises a third sub-block comprising a third memory cell, a third bit line coupled to a drain of the third memory cell, and a third source line coupled to a source of the third memory cell. The second block also includes a fourth sub-block which includes a fourth memory cell, a fourth bit line coupled to a drain of the fourth memory cell, and a fourth source line coupled to a source of the fourth memory cell.

Abstract: A circuit to ensure that a flash memory device with a write state machine ("WSM") and address transition detection ("ATD") provides correct data after a write/erase step, after an erase suspend command is issued or when the device comes out of deep power-down mode. Whenever the WSM takes control of the device the ATD circuits are disabled. When the WSM relinquishes control over the read path it enables ATD by deasserting the disable ATD bar ("DATDB") signal. An internal signal that is a logical inversion of the chip enable bar ("CEB") input is used along with the DATDB signal to generate ATD pulses. Hence, if the user presents a valid address at the address pins with CEB held deasserted when entering the erase suspend mode, the deassertion of the DATDB by the WSM will generate an ATD pulse and valid data will be presented on output pads of the device after an access time.