Abstract: A memory system in which the sequence in which consecutive functions are performed is controlled by sensing the completion of each function before initiating the performance of the next function in the sequence. Sequencing of the functions is made dependent on the internal delays of the memory system, thereby eliminating the need for clocking signals.

Abstract: A circuit adapted to receive at its input terminal signals having either a first or a second value includes a level shifting transistor for shifting the second value signals at its input terminal to a third value, where the second value is intermediate the first and third values. The transistor is turned on and off as a function of the voltage at a first node at which is produced the inverse of the input signals. An output terminal is coupled to the first node for one value of input signal and is decoupled from it for the other value of input signal. Decoupling enables the level shift transistor to always be operated as a function of the input signal while enabling signals incompatible with the signal at the first node, produced by other circuitry, to be present at, or applied to, the output terminal.