Patents by Inventor Peter K. Moon
Peter K. Moon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9984922Abstract: Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect.Type: GrantFiled: September 1, 2016Date of Patent: May 29, 2018Assignee: Intel CorporationInventors: Jun He, Kevin J. Fischer, Ying Zhou, Peter K. Moon
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Publication number: 20160372366Abstract: Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect.Type: ApplicationFiled: September 1, 2016Publication date: December 22, 2016Inventors: Jun HE, Kevin J. FISCHER, Ying ZHOU, Peter K. MOON
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Patent number: 9437545Abstract: Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect.Type: GrantFiled: December 12, 2014Date of Patent: September 6, 2016Assignee: Intel CorporationInventors: Jun He, Kevin J. Fischer, Ying Zhou, Peter K. Moon
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Publication number: 20150097292Abstract: Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect.Type: ApplicationFiled: December 12, 2014Publication date: April 9, 2015Inventors: Jun HE, Kevin J. FISCHER, Ying ZHOU, Peter K. MOON
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Patent number: 8928125Abstract: Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect.Type: GrantFiled: September 23, 2011Date of Patent: January 6, 2015Assignee: Intel CorporationInventors: Jun He, Kevin J. Fischer, Ying Zhou, Peter K. Moon
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Publication number: 20120007242Abstract: Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect.Type: ApplicationFiled: September 23, 2011Publication date: January 12, 2012Inventors: Jun He, Kevin J. Fischer, Ying Zhou, Peter K. Moon
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Patent number: 8058710Abstract: Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect.Type: GrantFiled: March 28, 2008Date of Patent: November 15, 2011Assignee: Intel CorporationInventors: Jun He, Kevin J. Fischer, Ying Zhou, Peter K. Moon
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Patent number: 7629268Abstract: In one embodiment, an apparatus comprises a first layer having at least one interconnect formed in an interlayer dielectric (ILD), a second layer formed over the first layer having a second at least one interconnect, a third layer formed over the second layer, the third layer defining at least one air gap between the second at least one interconnect and the third layer, and at least one shunt selectively covering the first and second at least one interconnects. In another embodiment, a method comprises forming a first layer comprising an ILD and a first at least one interconnect, forming a second layer over the first layer, the second layer having a second at least one interconnect, depositing at least one shunt over the first and second at least one interconnects, forming a third layer over the second layer, and evaporating a portion of the second layer to create at least one air gap between the second at least one interconnect and the third layer.Type: GrantFiled: August 15, 2007Date of Patent: December 8, 2009Assignee: Intel CorporationInventors: Valery M. Dubin, Peter K. Moon
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Patent number: 7586196Abstract: In one embodiment, an apparatus comprises a first layer having at least one interconnect formed in an interlayer dielectric (ILD), a second layer formed over the first layer having a second at least one interconnect, a third layer formed over the second layer, the third layer defining at least one air gap between the second at least one interconnect and the third layer, and at least one shunt selectively covering the first and second at least one interconnects. In another embodiment, a method comprises forming a first layer comprising an ILD and a first at least one interconnect, forming a second layer over the first layer, the second layer having a second at least one interconnect, depositing at least one shunt over the first and second at least one interconnects, forming a third layer over the second layer, and evaporating a portion of the second layer to create at least one air gap between the second at least one interconnect and the third layer.Type: GrantFiled: August 15, 2007Date of Patent: September 8, 2009Assignee: Intel CorporationInventors: Valery M. Dubin, Peter K. Moon
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Publication number: 20090117733Abstract: The present invention includes a method of providing a substrate; sequentially forming a seed layer over the substrate and forming a protection layer over the seed layer; and sequentially removing the protection layer and forming a conductor over the seed layer. The present invention further includes a structure having a substrate, the substrate having a device; an insulator disposed over the substrate, the insulator having an opening, the opening disposed over the device; a barrier layer disposed over the opening; a seed layer disposed over the barrier layer; and a protection layer disposed over the seed layer.Type: ApplicationFiled: December 24, 2008Publication date: May 7, 2009Inventors: Valery M. Dubin, Peter K. Moon
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Patent number: 7525196Abstract: The present invention includes a method of providing a substrate; sequentially forming a seed layer over the substrate and forming a protection layer over the seed layer; and sequentially removing the protection layer and forming a conductor over the seed layer. The present invention further includes a structure having a substrate, the substrate having a device; an insulator disposed over the substrate, the insulator having an opening, the opening disposed over the device; a barrier layer disposed over the opening; a seed layer disposed over the barrier layer; and a protection layer disposed over the seed layer.Type: GrantFiled: January 19, 2006Date of Patent: April 28, 2009Assignee: Intel CorporationInventors: Valery M. Dubin, Peter K. Moon
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Publication number: 20080179748Abstract: Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect.Type: ApplicationFiled: March 28, 2008Publication date: July 31, 2008Inventors: Jun He, Kevin J. Fischer, Ying Zhou, Peter K. Moon
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Patent number: 7402519Abstract: Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect.Type: GrantFiled: June 3, 2005Date of Patent: July 22, 2008Assignee: Intel CorporationInventors: Jun He, Kevin J. Fischer, Ying Zhou, Peter K. Moon
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Patent number: 7326981Abstract: Embodiments of the invention provide a method for producing ferroelectric polymer devices (FPMDs) employing conditions that avoid or reduce detrimental impact on the ferroelectric polymer film. For one embodiment, a damascene patterning metallization technique is used. For one embodiment a first metal layer is deposited on a substrate to form the bottom electrode for the FPMD. The first metal layer is capped with a selectively deposited diffusion barrier. A layer of ferroelectric polymer film is then deposited on the first conductive layer. The ferroelectric polymer film is planarized. A second metal layer is deposited on the ferroelectric polymer film layer to form the top electrode of the FPMD. The second metal layer is deposited such that the ferroelectric polymer film is not substantially degraded. For various alternative embodiments the various component processes may be accomplished at temperatures far below those employed in a conventional damascene patterning metallization process.Type: GrantFiled: March 9, 2006Date of Patent: February 5, 2008Assignee: Intel CorporationInventors: Makarem A. Hussein, Ebrahim Andideh, Peter K. Moon, Daniel C. Diana
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Patent number: 7304388Abstract: In one embodiment, an apparatus comprises a first layer having at least one interconnect formed in an interlayer dielectric (ILD), a second layer formed over the first layer having a second at least one interconnect, a third layer formed over the second layer, the third layer defining at least one air gap between the second at least one interconnect and the third layer, and at least one shunt selectively covering the first and second at least one interconnects. In another embodiment, a method comprises forming a first layer comprising an ILD and a first at least one interconnect, forming a second layer over the first layer, the second layer having a second at least one interconnect, depositing at least one shunt over the first and second at least one interconnects, forming a third layer over the second layer, and evaporating a portion of the second layer to create at least one air gap between the second at least one interconnect and the third layer.Type: GrantFiled: June 26, 2003Date of Patent: December 4, 2007Assignee: Intel CorporationInventors: Valery M. Dubin, Peter K. Moon
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Patent number: 7239019Abstract: An inter-layer dielectric structure and method of making such structure are disclosed. A composite dielectric layer, initially comprising a porous matrix and a porogen, is formed. Subsequent to other processing treatments, the porogen is decomposed and removed from at least a portion of the porous matrix, leaving voids defined by the porous matrix in areas previously occupied by the porogen. The resultant structure has a desirably low k value as a result of the porosity and materials comprising the porous matrix and porogen. The composite dielectric layer may be used in concert with other dielectric layers of varying porosity, dimensions, and material properties to provide varied mechanical and electrical performance profiles.Type: GrantFiled: June 28, 2005Date of Patent: July 3, 2007Assignee: Intel CorporationInventors: Jihperng Leu, Grant M. Kloster, David H. Gracias, Lee D. Rockford, Peter K. Moon, Chris E. Barns
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Patent number: 7223694Abstract: A method of depositing a metal cladding on conductors in a damascene process is described. The potential between, for instance, cobalt ions in electroless solution and the surface of an ILD between the conductors is adjusted so as to repel the metal from the ILD.Type: GrantFiled: June 10, 2003Date of Patent: May 29, 2007Assignee: Intel CorporationInventors: Chin-Chang Cheng, Valery M. Dubin, Peter K. Moon
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Patent number: 7078754Abstract: Embodiments of the invention provide a method for producing ferroelectric polymer devices (FPMDs) employing conditions that avoid or reduce detrimental impact on the ferroelectric polymer film. For one embodiment, a damascene patterning metallization technique is used. For one embodiment a first metal layer is deposited on a substrate to form the bottom electrode for the FPMD. The first metal layer is capped with a selectively deposited diffusion barrier. A layer of ferroelectric polymer film is then deposited on the first conductive layer. The ferroelectric polymer film is planarized. A second metal layer is deposited on the ferroelectric polymer film layer to form the top electrode of the FPMD. The second metal layer is deposited such that the ferroelectric polymer film is not substantially degraded. For various alternative embodiments the various component processes may be accomplished at temperatures far below those employed in a conventional damascene patterning metallization process.Type: GrantFiled: December 7, 2004Date of Patent: July 18, 2006Assignee: Intel CorporationInventors: Makarem A. Hussein, Ebrahim Andideh, Peter K. Moon, Daniel C. Diana
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Patent number: 7060617Abstract: The present invention includes a method of providing a substrate; sequentially forming a seed layer over the substrate and forming a protection layer over the seed layer; and sequentially removing the protection layer and forming a conductor over the seed layer. The present invention further includes a structure having a substrate, the substrate having a device; an insulator disposed over the substrate, the insulator having an opening, the opening disposed over the device; a barrier layer disposed over the opening; a seed layer disposed over the barrier layer; and a protection layer disposed over the seed layer.Type: GrantFiled: June 28, 2002Date of Patent: June 13, 2006Assignee: Intel CorporationInventors: Valery M. Dubin, Peter K. Moon
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Patent number: 7018918Abstract: An inter-layer dielectric structure and method of making such structure are disclosed. A composite dielectric layer, initially comprising a porous matrix and a porogen, is formed. Subsequent to other processing treatments, the porogen is decomposed and removed from at least a portion of the porous matrix, leaving voids defined by the porous matrix in areas previously occupied by the porogen. The resultant structure has a desirably low k value as a result of the porosity and materials comprising the porous matrix and porogen. The composite dielectric layer may be used in concert with other dielectric layers of varying porosity, dimensions, and material properties to provide varied mechanical and electrical performance profiles.Type: GrantFiled: November 3, 2003Date of Patent: March 28, 2006Assignee: Intel CorporationInventors: Grant M. Kloster, Kevin P. O'brien, Michael D. Goodner, Jihperng Leu, David H. Gracias, Lee D. Rockford, Peter K. Moon, Chris E. Barns