Abstract: A bias voltage generator circuit may include a mode control circuit, a clock generator circuit coupled with the mode control unit and configured to generate a plurality of clock signals, and a charge pump circuit configured to receive the clock signals. The charge pump circuit may be coupled with the mode control circuit and operable to output selectable output voltages according to input from the mode control circuit. The output selectable voltages may depend upon the clock signals.

Abstract: A bias voltage generator circuit may include a mode control circuit, a clock generator circuit coupled with the mode control unit and configured to generate a plurality of clock signals, and a charge pump circuit configured to receive the clock signals. The charge pump circuit may be coupled with the mode control circuit and operable to output selectable output voltages according to input from the mode control circuit. The output selectable voltages may depend upon the clock signals.

Abstract: A bias voltage generator circuit may include a mode control circuit, a clock generator circuit coupled with the mode control unit and configured to generate a plurality of clock signals, and a charge pump circuit configured to receive the clock signals. The charge pump circuit may be coupled with the mode control circuit and operable to output selectable output voltages according to input from the mode control circuit. The output selectable voltages may depend upon the clock signals.

Abstract: A digital-to-analog converter (DAC) and memory device includes an array of memory cells including resistive memory elements programmable between a high resistive and low resistive state. In implementations the array of memory cells is segmented into unary and binary coded sub-arrays. The device includes a binarizer configured to couple to the memory array to assign binary weights, or segmented unary and binary weights, to currents through a plurality of memory cells or voltages across a plurality of memory cells. The memory device further includes a summer to sum the weighted outputs of the binarizer. A current to voltage converter coupled with the summer generates an analog output voltage corresponding with digital data stored in a plurality of memory cells.

Abstract: A bias voltage generator circuit may include a mode control circuit, a clock generator circuit coupled with the mode control unit and configured to generate a plurality of clock signals, and a charge pump circuit configured to receive the clock signals. The charge pump circuit may be coupled with the mode control circuit and operable to output selectable output voltages according to input from the mode control circuit. The output selectable voltages may depend upon the clock signals.

Abstract: A resistive memory device. Implementations may include an array of memory cells including resistive memory elements which are coupled to isolation transistors and which may include a magnetic tunnel junction. A decoder decodes input address information to select a row of the array. A binarizer coupled to the memory array assigns binary weights to outputs of the memory array output through bit lines coupled to the memory cells. A summer sums the binary weighted outputs, and a quantizer generates an output digital code corresponding to data stored in a plurality of memory cells during a prior program cycle. The outputs of the memory array may be currents or voltages. In implementations multiple arrays of memory cells may be utilized and their respective outputs combined to form higher bit outputs, such as eight bit, twelve bit, sixteen bit, and so forth.

Abstract: A resistive memory device. Implementations may include an array of memory cells including resistive memory elements which are coupled to isolation transistors and which may include a magnetic tunnel junction. A decoder decodes input address information to select a row of the array. A binarizer coupled to the memory array assigns binary weights to outputs of the memory array output through bit lines coupled to the memory cells. A summer sums the binary weighted outputs, and a quantizer generates an output digital code corresponding to data stored in a plurality of memory cells during a prior program cycle. The outputs of the memory array may be currents or voltages. In implementations multiple arrays of memory cells may be utilized and their respective outputs combined to form higher bit outputs, such as eight bit, twelve bit, sixteen bit, and so forth.

Abstract: A resistive memory device. Implementations may include an array of memory cells including resistive memory elements which are coupled to isolation transistors and which may include a magnetic tunnel junction. A decoder decodes input address information to select a row of the array. A binarizer coupled to the memory array assigns binary weights to outputs of the memory array output through bit lines coupled to the memory cells. A summer sums the binary weighted outputs, and a quantizer generates an output digital code corresponding to data stored in a plurality of memory cells during a prior program cycle. The outputs of the memory array may be currents or voltages. In implementations multiple arrays of memory cells may be utilized and their respective outputs combined to form higher bit outputs, such as eight bit, twelve bit, sixteen bit, and so forth.