Abstract: A digital PLL circuit has a serial shift register receiving input pulses and producing time-delayed output pulses, a clock generator applying clock pulses to the shift register to drive it and set the phase shift of the output pulses, and a digitally-controlled potentiometer connected in series with the clock generator and being adjustable to change its resistance in increments in order to adjust the resistance of the clock generator and thereby set the frequency of the clock pulses applied to the shift register and the time delay produced by the shift register. A feedback control arrangement receives the same digital input pulses as received by the shift register and detects the periods of the input pulses by counting to produce control pulses proportional to the detected periods. A ROM unit stores a look-up table of values representing an array of different counts of increments by which the potentiometer resistance can be adjusted.