Abstract: The present invention discloses a circuit that reduces the transmission delay of the redundancy evaluation for SDRAM. After an input address is decoded as an external address, the external address is routed to a global factor generator to generate global factors accompanied with an address strobe pulse. The external address is also routed to a redundancy check circuit for starting the redundancy evaluation. Therefore, the redundancy evaluation can be performed as soon as the external address comes. While the external address comes, a column burst pulse and a system clock are directed to the internal counter of the global factor generator for counting continuously. The current count value is treated as an internal address and then routed to the redundancy check circuit to output the ready redundancy evaluation.