Abstract: A circuit arrangement for reducing noise when peaking the edges of a useful signal (S1) by combination with a peaking signal (S3) derived therefrom, which signal only influences the useful signal (S1) when a predetermined amplitude threshold is exceeded, which arrangement has a peaking signal stage (20) for supplying the peaking signal (S3) and a noise suppression stage (7) in which a noise suppression signal is generated and is superimposed on the peaking signal (S3), while the peaking signal stage (20) applies the peaking signal (S3) to two push-pull current outputs (21, 22) provides the possibility of a very simple circuit structure, particularly with a view to a space-saving integration on a semiconductor crystal in that each of the push-pull current outputs (21, 22) in the noise suppression stage (7) is connected to a series resistor (23, 24) and to the control terminal of one of two transistors (25, 26) whose main current paths at one end are connected together and to a supply current source (27) and at

Abstract: Control circuit for calibrating a delay line for a television receiver. The delay line contains series-connected all-pass sections of at least 2nd-order, the inductances of which are replaced by gyrators to which capacitances are connected. During at least one line of the vertical blanking period, the delay line is included into a phase-lock loop for comparison with a line-frequency signal in order to control the delay time of the all-pass sections.