Patents by Inventor Peter Kinget
Peter Kinget has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230246649Abstract: Phase interpolators are provided, the phase interpolators including: a first phase interpolator having a first output that outputs a first interpolated clock signal based on quadrature clock signals and a first phase interpolator control signal; a second phase interpolator having a second output that outputs a second interpolated clock signal based on the quadrature clock signals and a second phase interpolator control signal that is shifted from the first phase interpolator control signal by half of an integral nonlinearity (INL) period of the first phase interpolator; and a phase combiner that outputs a third interpolated clock signal based on the first interpolated clock signal and the second interpolated clock signal. In some of these embodiments, the phase interpolators further comprise a first amplitude limiter that receives the first interpolated clock signal and outputs a first amplitude-limited interpolated clock signal that is provided to the phase combiner.Type: ApplicationFiled: January 30, 2023Publication date: August 3, 2023Inventors: Zhaowen Wang, Peter Kinget
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Publication number: 20220244755Abstract: Circuits and methods for multi-phase clock generators and phase interpolators are provided. The multi-phase clock generators include a delay line and multi-phase injection locked oscillator. At each stage of the multi-phase injection locked oscillator, injection currents are provided from a corresponding stage of the delay line. Outputs of the multi-phase injection locked oscillator and provided to mixers which produce inputs to an operational transconductance amplifier which provides feedback to the delay line and the multi-phase injection locked oscillator. The phase interpolator uses a technique of flipping certain input clock signals to reduce the number of components required while still being able to interpolate phase over 360 degrees and to reduce noise.Type: ApplicationFiled: February 4, 2022Publication date: August 4, 2022Inventors: Zhaowen Wang, Yudong Zhang, Peter Kinget
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Patent number: 10833694Abstract: In accordance with some embodiments, polarity-coincidence, adaptive time-delay estimation (PCC-ATDE), mixed-signal techniques are provided. In some embodiments, these techniques use 1-bit quantized signals and negative-feedback architectures to directly determine a time-delay between signals at analog inputs and convert the time-delay to a digital number.Type: GrantFiled: April 8, 2019Date of Patent: November 10, 2020Assignee: The Trustees of Columbia University in the City of New YorkInventors: Daniel De Godoy Peixoto, Xiaofan Jiang, Peter Kinget
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Publication number: 20190312582Abstract: In accordance with some embodiments, polarity-coincidence, adaptive time-delay estimation (PCC-ATDE), mixed-signal techniques are provided. In some embodiments, these techniques use 1-bit quantized signals and negative-feedback architectures to directly determine a time-delay between signals at analog inputs and convert the time-delay to a digital number.Type: ApplicationFiled: April 8, 2019Publication date: October 10, 2019Inventors: Daniel De Godoy Peixoto, Xiaofan Jiang, Peter Kinget
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Publication number: 20190140621Abstract: An electrical circuit assembly can include a semiconductor integrated circuit, such as fabricated including CMOS devices. A first lateral-mode resonator can be fabricated upon a surface of the semiconductor integrated circuit, such as including a deposited acoustic energy storage layer including a semiconductor material, a deposited piezoelectric layer acoustically coupled to the deposited acoustic energy storage layer, and a first conductive region electrically coupled to the deposited piezoelectric layer and electrically coupled to the semiconductor integrated circuit. The semiconductor integrated circuit can include one or more transistor structures, such as fabricated prior to fabrication of the lateral-mode resonator. Fabrication of the lateral-mode resonator can include low-temperature processing specified to avoid disrupting operational characteristics of the transistor structures.Type: ApplicationFiled: September 28, 2018Publication date: May 9, 2019Inventors: Hassan Edrees, Ioannis Kymissis, Peter Kinget
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Patent number: 10122345Abstract: An electrical circuit assembly can include a semiconductor integrated circuit, such as fabricated including CMOS devices. A first lateral-mode resonator can be fabricated upon a surface of the semiconductor integrated circuit, such as including a deposited acoustic energy storage layer including a semiconductor material, a deposited piezoelectric layer acoustically coupled to the deposited acoustic energy storage layer, and a first conductive region electrically coupled to the deposited piezoelectric layer and electrically coupled to the semiconductor integrated circuit. The semiconductor integrated circuit can include one or more transistor structures, such as fabricated prior to fabrication of the lateral-mode resonator. Fabrication of the lateral-mode resonator can include low-temperature processing specified to avoid disrupting operational characteristics of the transistor structures.Type: GrantFiled: June 26, 2014Date of Patent: November 6, 2018Assignee: The Trustees of Columbia University in the City of New YorkInventors: Hassan Edrees, Ioannis Kymissis, Peter Kinget
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Patent number: 9654126Abstract: Systems comprising: a first MDAC stage comprising: a sub-ADC that outputs a value based on an input signal; at least two reference capacitors that are charged to a Vref; at least two sampling capacitors that are charged to a Vin; and a plurality of switches that couple the at least two reference capacitors so that they are charged during a sampling phase, that couple the at least two sampling capacitors so that they are charged during the sampling phase, that couple at least one of the reference capacitors so that it is parallel to one of the at least two sampling capacitors during a hold phase, and that couple the other of the at least two sampling capacitors so that it couples the at least one of the reference capacitors and the one of the at least two sampling capacitors to a reference capacitor of a second MDAC stage.Type: GrantFiled: September 21, 2015Date of Patent: May 16, 2017Assignee: The Trustees of Columbia University in the City of New YorkInventors: Jayanth Kuppambatti, Junhua Shen, Peter Kinget
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Publication number: 20160358672Abstract: Circuits for estimating threshold voltages of transistors in memory device bitcells are provided. The circuits use a multiplexer, a sensor switch network, a power switch network, and an NMOS device configured as a sensor to couple a desired one the transistors in the bitcells and the NMOS device to each other, to a test voltage, and to ground. A sensor voltage node can then be measured, and based on the resulting measurement, a threshold voltage for the transistor estimate.Type: ApplicationFiled: August 22, 2016Publication date: December 8, 2016Applicant: The Trustees of Columbia University in the City of New YorkInventors: Mingoo Seok, Peter Kinget, Teng Yang
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Patent number: 9424952Abstract: Circuits for estimating threshold voltages of transistors in memory device bitcells are provided. The circuits use a multiplexer, a sensor switch network, a power switch network, and an NMOS device configured as a sensor to couple a desired one the transistors in the bitcells and the NMOS device to each other, to a test voltage, and to ground. A sensor voltage node can then be measured, and based on the resulting measurement, a threshold voltage for the transistor estimate.Type: GrantFiled: February 8, 2016Date of Patent: August 23, 2016Assignee: The Trustees of Columbia University in the City of New YorkInventors: Mingoo Seok, Peter Kinget, Teng Yang
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Publication number: 20160232986Abstract: Circuits for estimating threshold voltages of transistors in memory device bitcells are provided. The circuits use a multiplexer, a sensor switch network, a power switch network, and an NMOS device configured as a sensor to couple a desired one the transistors in the bitcells and the NMOS device to each other, to a test voltage, and to ground. A sensor voltage node can then be measured, and based on the resulting measurement, a threshold voltage for the transistor estimate.Type: ApplicationFiled: February 8, 2016Publication date: August 11, 2016Inventors: Mingoo Seok, Peter Kinget, Teng Yang
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Publication number: 20160191017Abstract: An electrical circuit assembly can include a semiconductor integrated circuit, such as fabricated including CMOS devices. A first lateral-mode resonator can be fabricated upon a surface of the semiconductor integrated circuit, such as including a deposited acoustic energy storage layer including a semiconductor material, a deposited piezoelectric layer acoustically coupled to the deposited acoustic energy storage layer, and a first conductive region electrically coupled to the deposited piezoelectric layer and electrically coupled to the semiconductor integrated circuit. The semiconductor integrated circuit can include one or more transistor structures, such as fabricated prior to fabrication of the lateral-mode resonator. Fabrication of the lateral-mode resonator can include low-temperature processing specified to avoid disrupting operational characteristics of the transistor structures.Type: ApplicationFiled: June 26, 2014Publication date: June 30, 2016Inventors: Hassan EDREES, Ioannis KYMISSISS, Peter KINGET
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Patent number: 9246504Abstract: Circuits and methods for implementing a residue amplifier are provided. In some embodiments, circuits for implementing a residue amplifier are provided, the circuits comprising: a first capacitor configured to be charged to an input voltage level and that discharges from the input voltage level to a reference voltage level; a comparator having a first input coupled to the first capacitor, a second input coupled to a reference voltage source, and an output that indicates when the charge on the first capacitor is above the reference voltage level; and a second capacitor configured to be charged to an output voltage based on the output of the comparator.Type: GrantFiled: December 12, 2011Date of Patent: January 26, 2016Assignee: The Trustees of Columbia University in the City of New YorkInventors: Junhua Shen, Peter Kinget
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Publication number: 20160013803Abstract: Systems comprising: a first MDAC stage comprising: a sub-ADC that outputs a value based on an input signal; at least two reference capacitors that are charged to a Vref; at least two sampling capacitors that are charged to a Vin; and a plurality of switches that couple the at least two reference capacitors so that they are charged during a sampling phase, that couple the at least two sampling capacitors so that they are charged during the sampling phase, that couple at least one of the reference capacitors so that it is parallel to one of the at least two sampling capacitors during a hold phase, and that couple the other of the at least two sampling capacitors so that it couples the at least one of the reference capacitors and the one of the at least two sampling capacitors to a reference capacitor of a second MDAC stage.Type: ApplicationFiled: September 21, 2015Publication date: January 14, 2016Inventors: Jayanth Kuppambatti, Junhua Shen, Peter Kinget
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Patent number: 9154244Abstract: In accordance with some embodiments, methods for controlling the second order intercept point in a receiver are provided, the methods comprising: generating an amplitude modulated test tone; causing the test tone to be received by a receiver; determining a characteristic of a second order intercept point of the receiver based on the received test tone; and based on the characteristic, adjusting a parameter of the receiver. In accordance with some embodiments, systems for controlling the second order intercept point in as receiver are provided, the systems comprising: a test tone generator that generates an amplitude modulated test tone; a receiver that receives the test tone; a correlator that determines a characteristic of a second order intercept point of the receiver based on the received test tone; and digital logic that, based on the characteristic, adjusts a parameter of the receiver.Type: GrantFiled: August 29, 2014Date of Patent: October 6, 2015Assignee: The Trustees of Columbia University in the City of New YorkInventors: Yiping Feng, Peter Kinget
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Patent number: 9143144Abstract: Systems comprising: a first MDAC stage comprising: a sub-ADC that outputs a value based on an input signal; at least two reference capacitors that are charged to a Vref; at least two sampling capacitors that are charged to a Vin; and a plurality of switches that couple the at least two reference capacitors so that they are charged during a sampling phase, that couple the at least two sampling capacitors so that they are charged during the sampling phase, that couple at least one of the reference capacitors so that it is parallel to one of the at least two sampling capacitors during a hold phase, and that couple the other of the at least two sampling capacitors so that it couples the at least one of the reference capacitors and the one of the at least two sampling capacitors to a reference capacitor of a second MDAC stage.Type: GrantFiled: March 19, 2012Date of Patent: September 22, 2015Assignee: The Trustees of Columbia University in the City of New YorkInventors: Jayanth Kuppambatti, Junhua Shen, Peter Kinget
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Publication number: 20150056937Abstract: In accordance with some embodiments, methods for controlling the second order intercept point in a receiver are provided, the methods comprising: generating an amplitude modulated test tone; causing the test tone to be received by a receiver; determining a characteristic of a second order intercept point of the receiver based on the received test tone; and based on the characteristic, adjusting a parameter of the receiver. In accordance with some embodiments, systems for controlling the second order intercept point in as receiver are provided, the systems comprising: a test tone generator that generates an amplitude modulated test tone; a receiver that receives the test tone; a correlator that determines a characteristic of a second order intercept point of the receiver based on the received test tone; and digital logic that, based on the characteristic, adjusts a parameter of the receiver.Type: ApplicationFiled: August 29, 2014Publication date: February 26, 2015Inventors: Yiping Feng, Peter Kinget
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Patent number: 8849227Abstract: In accordance with some embodiments, methods for controlling the second order intercept point in a receiver are provided, the methods comprising: generating an amplitude modulated test tone; causing the test tone to be received by a receiver; determining a characteristic of a second order intercept point of the receiver based on the received test tone; and based on the characteristic, adjusting a parameter of the receiver. In accordance with some embodiments, systems for controlling the second order intercept point in a receiver are provided, the systems comprising: a test tone generator that generates an amplitude modulated test tone; a receiver that receives the test tone; a correlator that determines a characteristic of a second order intercept point of the receiver based on the received test tone; and digital logic that, based on the characteristic, adjusts a parameter of the receiver.Type: GrantFiled: September 28, 2010Date of Patent: September 30, 2014Assignee: The Trustees of Columbia University in the City of New YorkInventors: Yiping Feng, Peter Kinget
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Publication number: 20140197971Abstract: Systems comprising: a first MDAC stage comprising: a sub-ADC that outputs a value based on an input signal; at least two reference capacitors that are charged to a Vref; at least two sampling capacitors that are charged to a Vin; and a plurality of switches that couple the at least two reference capacitors so that they are charged during a sampling phase, that couple the at least two sampling capacitors so that they are charged during the sampling phase, that couple at least one of the reference capacitors so that it is parallel to one of the at least two sampling capacitors during a hold phase, and that couple the other of the at least two sampling capacitors so that it couples the at least one of the reference capacitors and the one of the at least two sampling capacitors to a reference capacitor of a second MDAC stage.Type: ApplicationFiled: March 19, 2012Publication date: July 17, 2014Inventors: Jayanth Kuppambatti, Junhua Shen, Peter Kinget
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Publication number: 20140132438Abstract: Circuits and methods for implementing a residue amplifier are provided. In some embodiments, circuits for implementing a residue amplifier are provided, the circuits comprising: a first capacitor configured to be charged to an input voltage level and that discharges from the input voltage level to a reference voltage level; a comparator having a first input coupled to the first capacitor, a second input coupled to a reference voltage source, and an output that indicates when the charge on the first capacitor is above the reference voltage level; and a second capacitor configured to be charged to an output voltage based on the output of the comparator.Type: ApplicationFiled: December 12, 2011Publication date: May 15, 2014Inventors: Junhua Shen, Peter Kinget
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Patent number: 8699627Abstract: In accordance with some embodiments, receivers for receiving a wireless data transmission are provided, the receivers comprising at least one amplifier that receives an RF input signal and produces at least one amplified signal; a mixer that mixes the at least one signal to produce a mixed signal; a filter that filters the mixed signal to produce a filtered signal, a comparator that compares the filtered signal to a threshold voltage and produces a digital signal, a first pulse generate i that generates a first pulse in response to a transition in the digital signal, a second pulse generator that generates a second pulse that is longer than the first pulse in response to a transition in the digital signal; and digital logic that generates a clock output and that generates a data output based on a state of the first pulse when the second pulse expires.Type: GrantFiled: September 28, 2010Date of Patent: April 15, 2014Assignee: The Trustee of Columbia University in the City of New YorkInventors: Marco Crepaldi, Peter Kinget