Patents by Inventor Peter Klapproth

Peter Klapproth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8466723
    Abstract: A data processing system comprises a plurality of sub-circuits, a clock generator provided with a control circuit, a pool of oscillator circuits comprising at least three oscillator circuits, and a multiplexing circuit coupled between the pool and clock inputs of the sub-circuits. The multiplexing circuit has a control input coupled to a control output of the control circuit. The multiplexing circuit is configured to couple any selectable one of the oscillator circuits in the pool to a clock input of each of the sub-circuits. The control circuit is configured to set the frequencies of respective ones of the clock circuit by controlling the multiplexing circuit to supply clock signals derived from selected ones of the oscillator circuits to the sub-circuits.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: June 18, 2013
    Assignee: Synopsys, Inc.
    Inventors: Peter Klapproth, Greg Ehmann, Neal Wingen
  • Patent number: 8364860
    Abstract: A data-processing system is described comprising: • A plurality of data-processing devices (11, 12, 13, 14) • A data-handling facility (20) shared by the data-processing devices, • An aggregation facility (30) for receiving signals (R1, R2, R3, R4) indicative for individual requirements from the data-processing devices for a performance of the shared data-handling facility and for providing a control signal (RA) indicative for a required activity level to meet the aggregated requirements, • a control device (40) for controlling an activity level of the data-handling facility depending on the control signal (RA). Additionally a data-processing method is described.
    Type: Grant
    Filed: September 18, 2008
    Date of Patent: January 29, 2013
    Assignee: NXP B.V.
    Inventors: Peter Klapproth, Greg Ehmann, Claus Pfeiffer
  • Publication number: 20110050300
    Abstract: A data processing system comprises a plurality of sub-circuits (10a, 10a, 10c), a clock generator (20) provided with a control circuit (22), a pool of oscillator circuits (24a, . . . 24f) comprising at least three oscillator circuits, and a multiplexing circuit (26) coupled between the pool and clock inputs of the sub-circuits. The multiplexing circuit has a control input (27) coupled to a control output (23) of the control circuit. The multiplexing circuit is configured to couple any selectable one of the oscillator circuits in the pool to a clock input (11a, 11b, 11c) of each of the sub-circuits. The control circuit (22) is configured to set the frequencies of respective ones of the clock circuit by controlling the multiplexing circuit to supply clock signals derived from selected ones of the oscillator circuits to the sub-circuits.
    Type: Application
    Filed: September 25, 2008
    Publication date: March 3, 2011
    Inventors: Peter Klapproth, Greg Ehmann, Neal Wingen
  • Publication number: 20100211702
    Abstract: A data-processing system is described comprising: A plurality of data-processing devices (11, 12, 13, 14) A data-handling facility (20) shared by the data-processing devices, An aggregation facility (30) for receiving signals (R1, R2, R3, R4) indicative for individual requirements from the data-processing devices for a performance of the shared data-handling facility and for providing a control signal (RA) indicative for a required activity level to meet the aggregated requirements, a control device (40) for controlling an activity level of the data-handling facility depending on the control signal (RA). Additionally a data-processing method is described.
    Type: Application
    Filed: September 18, 2008
    Publication date: August 19, 2010
    Applicant: NXP B.V.
    Inventors: Peter Klapproth, Greg Ehmann, Claus Pfeiffer
  • Patent number: 7433738
    Abstract: The invention relates to a device for muscle stimulation, said device comprising a pulse generator unit (9) for producing and sending an electrical stimulation pulse; a control unit (10) for controlling the pulse generator unit (9) in order to adjust the amplitude and the frequency of the stimulation pulses and to cause the transmission of stimulation pulses to a muscle to be stimulated; a detection unit (11) for detecting the instantaneous, spontaneous or stimulated cardiac rhythm of the carrier of the device; a housing (12) receiving the pulse generator unit (9), the control unit (10), and the detection unit (11); a counting unit (13) and a memory unit (14) for counting and storing the number of stimulation pulses emitted within a definable time interval; and a determination unit (15) for determining the arithmetic average of the stimulation frequency within the definable time interval.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: October 7, 2008
    Assignee: Fides Finanz-Invest GmbH & Co. KG
    Inventors: Peter Klapproth, Eckart Ulbrich
  • Publication number: 20060276855
    Abstract: The invention relates to a device for muscle stimulation, said device comprising a pulse generator unit (9) for producing and sending an electrical stimulation pulse; a control unit (10) for controlling the pulse generator unit (9) in order to adjust the amplitude and the frequency of the stimulation pulses and to cause the transmission of stimulation pulses to a muscle to be stimulated; a detection unit (11) for detecting the instantaneous, spontaneous or stimulated cardiac rhythm of the carrier of the device; a housing (12) receiving the pulse generator unit (9), the control unit (10), and the detection unit (11); a counting unit (13) and a memory unit (14) for counting and storing the number of stimulation pulses emitted within a definable time interval; and a determination unit (15) for determining the arithmetic average of the stimulation frequency within the definable time interval.
    Type: Application
    Filed: September 3, 2004
    Publication date: December 7, 2006
    Applicant: Fides Finanz-Invest GmbH & Co. KG
    Inventors: Peter Klapproth, Eckart Ulbrich
  • Patent number: 5828852
    Abstract: A method and a circuit configuration for operation of a bus system. A bus includes a bus control unit which controls only an arbitration and when time is exceeded during a data transmission. An actual data transmission is determined in a respective active master unit and an addressed slave unit. A characteristic of a bus cycle, such as a data length, access to a data area or a control area and a waiting cycle, is transmitted in encoded form through a multiplicity of control lines.
    Type: Grant
    Filed: November 27, 1995
    Date of Patent: October 27, 1998
    Assignees: Siemens Aktiengesellschaft, Advanced Risc Machines Ltd., Philips Electronics N.V., Inmos Ltd., Matra MHS S.A.
    Inventors: Thomas Niedermeier, Peter Rohm, Richard Schmid, David Flynn, Peter Klapproth, Frederik Zandveld, Jacobus Christophorus Koot, Andrew Michael Jones, James Graham Matthew, Bruno Douady
  • Patent number: 5590354
    Abstract: A microprocessor includes a processor element, a memory interface element, an IO interface element, a debug support element and an internal bus interconnecting all above elements. For easy debugging, it also includes attached to the internal bus a registered boundary scan standard (JTAG) interface that accesses one or more scan chains inside the microprocessor, and is arranged for controlling DMA-type exchanges via the internal bus with other elements connected to this bus.
    Type: Grant
    Filed: July 28, 1994
    Date of Patent: December 31, 1996
    Assignee: U.S. Philips Corporation
    Inventors: Peter Klapproth, Frederik Zandveld, Jacobus M. Bakker, Gerardus C. Van Loo
  • Patent number: 5163154
    Abstract: Microcontroller comprising in particular a central processing unit (10), a set of memories (11, 12), a specialized processing module (13) for performing, in sequence, operations on v variable operands and k operands of parameter type (constant during the sequence), and an arrangement of internal buses (20, 21) for the exchange of addresses and data.
    Type: Grant
    Filed: December 21, 1990
    Date of Patent: November 10, 1992
    Assignee: U.S. Philips Corp.
    Inventors: Jean-Pierre Bournas, Jean-Jacques Quisquater, Dominique De Waleffe, Peter Klapproth