Abstract: An apparatus and a method where a plurality of physically separate data receiving/analyzing elements receive data packets and time stamp these. A controlling unit determines a storing address for each data packet based on at least the time stamp, where the controlling unit does not perform the determination of the address until a predetermined time delay has elapsed after the time of receipt.

Abstract: An access system includes line cards. The line cards include first and second line cards. The first line card receives a first packet and includes a first interface control module that generates a first request signal to transfer the first packet. The first request signal includes an identifier of a second interface control module in the second line card. Crossbar modules are separate from the line cards and include first and second crossbar modules. The first crossbar module includes a first scheduler module. The second crossbar module transfers packets between a pair of the line cards. The packets include the first packet. The first scheduler module is separate from the line cards and, based on the first request signal, schedules the transfer of the packets from the first interface control module, through the second crossbar module, and to the second interface control module.

Abstract: An assembly and a method where a number of receiving units receive and store data in a number of queues de-queued by a plurality of processors/processes. If a selected queue for one processor has a fill level exceeding a limit, the packet is forwarded to a queue of another processor which is instructed to not de-queue that queue until the queue with the exceeded fill level has been emptied. Thus, load balancing between processes/processors may be obtained while maintaining an ordering between packets.

Abstract: An assembly where a number of receivers receiving packets for storing in queues in a storage and a means for de-queuing data from the storage. A controller determines addresses for the storage, the address being determined on the basis of at least a fill level of the queue(s), where information relating to de-queues addresses is only read-out when the fill-level(s) exceed a limit so as to not spend bandwidth on this information before it is required.

Abstract: An access system includes line cards. The line cards include first and second line cards. The first line card receives a first packet and includes a first interface control module that generates a first request signal to transfer the first packet. The first request signal includes an identifier of a second interface control module in the second line card. Crossbar modules are separate from the line cards and include first and second crossbar modules. The first crossbar module includes a first scheduler module. The second crossbar module transfers packets between a pair of the line cards. The packets include the first packet. The first scheduler module is separate from the line cards and, based on the first request signal, schedules the transfer of the packets from the first interface control module, through the second crossbar module, and to the second interface control module.

Abstract: An apparatus and a method where a plurality of physically separate data receiving/analyzing elements receive data packets and time stamp these. A controlling unit determines a storing address for each data packet based on at least the time stamp, where the controlling unit does not perform the determination of the address until a predetermined time delay has elapsed after the time of receipt.

Abstract: An assembly and a method where a number of receiving units receive and store data in a number of queues de-queued by a plurality of processors/processes. If a selected queue for one processor has a fill level exceeding a limit, the packet is forwarded to a queue of another processor which is instructed to not de-queue that queue until the queue with the exceeded fill level has been emptied. Thus, load balancing between processes/processors may be obtained while maintaining an ordering between packets.

Abstract: An assembly where a number of receivers receiving packets for storing in queues in a storage and a means for de-queuing data from the storage. A controller determines addresses for the storage, the address being determined on the basis of at least a fill level of the queue(s), where information relating to de-queues addresses is only read-out when the fill-level(s) exceed a limit so as to not spend bandwidth on this information before it is required.

Abstract: An apparatus including a plurality of first base circuits, a plurality of second base circuits, a first test circuit, a second test circuit, and a test path. The plurality of first base circuits may be coupled to the plurality of second base circuits via one or more base circuit paths on a layout. The first test circuit may be disposed in a first distal location of the layout. The second test circuit may be disposed in a second distal location of the layout. The test path may be configured to (i) couple the first test circuit to the second test circuit and (ii) generate a test time delay from the first test circuit to the second test circuit incrementally longer than a maximum time delay generated by any of the base circuit paths.

Abstract: A circuit comprising a register stack and a control circuit. The register stack may be configured as (i) a plurality of segments addressable through a segment address signal and (ii) a plurality of registers within each of the plurality of segments. The plurality of registers are generally addressable through a register address signal. The control circuit may be configured to (i) store a plurality of register states, (ii) store a segment count signal, and (iii) present the segment address signal responsive to the plurality of register states, the segment count signal, and the register address signal.

Abstract: An input/output characterization register is provided for characterizing an integrated circuit input or output. The register includes a normal data input, a characterization data input, and a data latch having a latch control input, a latch data input and a latch data output. The normal data input and the characterization data input are multiplexed with the latch data output to the latch data input.

Abstract: An apparatus including a first circuit and a second circuit. The first circuit may be configured to present a first data signal and a first indicator signal in response to a first clock signal and an enable signal. The second circuit may be configured to present a second data signal and a second indicator signal in response to the first data signal, the first indicator signal and a second clock signal.

Abstract: A memory controller for aligning write data and a clock strobe signal provided to a memory device includes a delay line coupled to a local clock input and providing as an output a delayed local clock signal. A first latch circuit receives data to be written to the memory device as an input and has an output coupled to a data input of the memory device. The first latch circuit is clocked by a first one of the local clock signal and the delayed local clock signal and provides in response the write data to the data input of the memory device. A clock strobe generating circuit is clocked by a second one of the local clock signal and the delayed local clock signal. The clock strobe generating circuit has an output coupled to a clock strobe input of the memory device and provides the clock strobe signal to the memory device.

Abstract: A system and method are presented for indicating active tag bits within valid entries of a dual-clock FIFO data buffer, used to transfer data between two clock domains. Data (containing tag bits) are written to the FIFO and read from the FIFO using separate clocks. Data writes are synchronous with the first clock, while reads are synchronous with the second clock. A FIFO entry is “valid” after data has been written to it, and before it is read. The system disclosed herein identifies the valid FIFO entries and generates a set of logic outputs, synchronized to the second clock (i.e., the read clock). Each output corresponds to one of the tag bit positions, and is HIGH if the corresponding tag bit is HIGH in any of the valid entries. This creates a means of detecting active tag bits in the FIFO without having to actually read each entry. Since the tag bits convey important information about the source and nature of the data, this detection system may expedite the data transfer.

Abstract: A method and apparatus are provided for testing linearity of two or more programmable delay chains in an integrated circuit. A first delay chain is successively programmed to a first sequence of delay settings and, for each delay setting in the first sequence, a second delay chain is successively programmed to a second sequence of delay settings. The second sequence sweeps a propagation delay through the second delay chain from a delay value less than a present propagation delay through the first delay chain to a delay value greater than the present propagation delay. For each delay setting of the second delay chain, a logic transition is applied to inputs of the first and second delay chains and the output of one of the first and second delay chains is latched as a function of the output of the other of the first and second delay chains to produce a sample value.

Abstract: A method and apparatus are provided for testing linearity of two or more programmable delay chains in an integrated circuit. A first delay chain is successively programmed to a first sequence of delay settings and, for each delay setting in the first sequence, a second delay chain is successively programmed to a second sequence of delay settings. The second sequence sweeps a propagation delay through the second delay chain from a delay value less than a present propagation delay through the first delay chain to a delay value greater than the present propagation delay. For each delay setting of the second delay chain, a logic transition is applied to inputs of the first and second delay chains and the output of one of the first and second delay chains is latched as a function of the output of the other of the first and second delay chains to produce a sample value.

Abstract: Methods and associated structure for realignment of returned read data from the memory component to the memory controller to adjust for phase shift in the memory device's supplied strobe signals due to propagation delays and other layout, fabrication and environmental factors. The realignment features of the present invention impose a calibrated delay on the memory controller's clock signal used to sample registered read data from the memory components. By so adjusting the alignment of returned read data with respect to the memory controller's clock, the present invention obviates the need for an asynchronous FIFO as is presently commonly practiced in the art to avoid such phase shifts between memory components and associated memory controller's.

Abstract: A memory controller for aligning write data and a clock strobe signal provided to a memory device includes a delay line coupled to a local clock input and providing as an output a delayed local clock signal. A first latch circuit receives data to be written to the memory device as an input and has an output coupled to a data input of the memory device. The first latch circuit is clocked by a first one of the local clock signal and the delayed local clock signal and provides in response the write data to the data input of the memory device. A clock strobe generating circuit is clocked by a second one of the local clock signal and the delayed local clock signal. The clock strobe generating circuit has an output coupled to a clock strobe input of the memory device and provides the clock strobe signal to the memory device.

Abstract: An input/output characterization register is provided for characterizing an integrated circuit input or output. The register includes a normal data input, a characterization data input, and a data latch having a latch control input, a latch data input and a latch data output. The normal data input and the characterization data input are multiplexed with the latch data output to the latch data input.

Abstract: A hardware description language (HDL) module is provided, which includes at least one input and output, including a clock input, a plurality of logic statements that define a function of the module, and a logic signal which is available within the module. The module further includes a synchronous assert check, which checks a state of the logic signal against a condition only during a predefined time window within a period of the clock input.