Abstract: A method of manufacturing a semiconductor device is provided including providing a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried insulation layer, forming a first transistor device on and in the SOI substrate in a logic area of the SOI substrate, removing the semiconductor layer and the buried insulation layer from a memory area of the SOI substrate, forming a dielectric layer on the exposed semiconductor bulk substrate, forming a floating gate layer on the first dielectric layer, forming an insulating layer on the floating gate layer and forming a control gate layer on the insulating layer, wherein an upper surface of the floating gate layer is substantially at the same height level as an upper surface of the semiconductor layer remaining in the logic area.

Abstract: A method of manufacturing a semiconductor device is provided including providing a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried insulation layer, forming a first transistor device on and in the SOI substrate in a logic area of the SOI substrate, removing the semiconductor layer and the buried insulation layer from a memory area of the SOI substrate, forming a dielectric layer on the exposed semiconductor bulk substrate, forming a floating gate layer on the first dielectric layer, forming an insulating layer on the floating gate layer and forming a control gate layer on the insulating layer, wherein an upper surface of the floating gate layer is substantially at the same height level as an upper surface of the semiconductor layer remaining in the logic area.

Abstract: A method comprises depositing a first portion of a first material layer on a semiconductor structure. A first run of a post-treatment process is performed for modifying at least the first portion of the first material layer. After the first run of the post-treatment process, a second portion of the first material layer is deposited. The second portion is formed of substantially the same material as the first portion. After the deposition of the second portion of the first material layer, a second run of the post-treatment process is performed for modifying at least the second portion of the first material layer.

Abstract: A method comprises depositing a first portion of a first material layer on a semiconductor structure. A first run of a post-treatment process is performed for modifying at least the first portion of the first material layer. After the first run of the post-treatment process, a second portion of the first material layer is deposited. The second portion is formed of substantially the same material as the first portion. After the deposition of the second portion of the first material layer, a second run of the post-treatment process is performed for modifying at least the second portion of the first material layer.

Abstract: A silicon wafer having no epitaxially deposited layer or layer produced by joining to the silicon wafer, with a nitrogen concentration of 1·1013-8·1014 atoms/cm3, an oxygen concentration of 5.2·1017-7.5·1017 atoms/cm3, a central thickness BMD density of 3·108-2·1010 cm?3, a cumulative length of linear slippages ?3 cm and a cumulative area of areal slippage regions ?7 cm2, the front surface having <45 nitrogen-induced defects of >0.13 ?m LSE in the DNN channel, a layer at least 5 ?m thick, in which ?1·104 COPs/cm3 with a size of ?0.09 ?m occur, and a BMD-free layer ?5 ?m thick. Such wafers may be produced by heat treating the silicon wafer, resting on a substrate holder, a specific substrate holder used depending on the wafer doping. For each holder, maximum heating rates are selected to avoid formation of slippages.

Abstract: A silicon wafer having no epitaxially deposited layer or layer produced by joining to the silicon wafer, with a nitrogen concentration of 1·1013-8·1014 atoms/cm3, an oxygen concentration of 5.2·1017-7.5·1017 atoms/cm3, a central thickness BMD density of 3·108-2·1010 cm?3, a cumulative length of linear slippages ?3 cm and a cumulative area of areal slippage regions ?7 cm2, the front surface having <45 nitrogen-induced defects of >0.13 ?m LSE in the DNN channel, a layer at least 5 ?m thick, in which ?1·104 COPs/cm3 with a size of ?0.09 ?m occur, and a BMD-free layer ?5 ?m thick. Such wafers may be produced by heat treating the silicon wafer, resting on a substrate holder, a specific substrate holder used depending on the wafer doping. For each holder, maximum heating rates are selected to avoid formation of slippages.

Abstract: A process for producing silicon wafers with low defect density is one wherein a) a silicon single crystal having an oxygen doping concentration of at least 4*10.sup.17 /cm.sup.3 is produced by molten material being solidified to form a single crystal and is then cooled, and the holding time of the single crystal during cooling in the temperature range of from 850.degree. C. to 1100.degree. C. is less than 80 minutes; b) the single crystal is processed to form silicon wafers; and c) the silicon wafers are annealed at a temperature of at least 1000.degree. C. for at least one hour. Also, it is possible to prepare a silicon single crystal based upon having an oxygen doping concentration of at least 4*10.sup.17 /cm.sup.3 and a nitrogen doping concentration of at least 1*10.sup.14 /cm.sup.3 for (a) above.