Abstract: Methods, systems, and devices related to sense amplifiers of a memory device serving as a Static Random Access Memory (SRAM) cache. For example, a memory array can be coupled to sense amplifiers. In a first mode, the sense amplifiers can be electrically disconnect from digit lines of the memory array. In the first mode, data and metadata of a cache line can be stored in the sense amplifiers when electrically disconnected from the number of digit lines. In the first mode, a portion of the data can be communicated, based on the metadata, from the sense amplifiers to the processing device. In a second mode, the sense amplifiers can connect to the memory array and sense data from the memory array.

Abstract: A processing unit of memory for table lookup is described herein. A plurality of elements (e.g., output values) of a lookup table (LUT) can be sequentially prefetched from a respective column of memory cells that is indicated by each vector value of vector values stored in positions of a register of the processing unit. Each of the vector values can be shifted by one position among the positions of the register to cause a terminal position of the register to be available for storing the respective output value among the prefetched output values.

Abstract: The processing unit (PU) PU of a memory device can receive a matrix of data values and a vector of data values stored in a bank. The PU can perform a first plurality of multiplication operations on a first data value of the vector utilizing a first plurality of data values of a first column of the matrix. The first plurality of multiplication operations can be performed by a plurality of multiply-accumulate (MAC) units. Each of the first plurality of multiplication operations can be performed by a different MAC unit of the plurality of MAC units. The PU can perform a second plurality of multiplication operations on a second data value of the vector utilizing a second plurality of data values of a second column of the matrix. Each of the second plurality of multiplication operations can be performed by a different MAC unit of the plurality of MAC units.

Abstract: A multiplexor (MUX) for a processing unit of memory is described herein. The MUX and a plurality of multiply-accumulate (MAC) units coupled to the MUX can receive a plurality of data values. The MUX can provide a first half of the plurality of data values to the plurality of MAC units during a first half of a duration of time and can provide a second half of the plurality of data values to the plurality of MAC units during a second half of the duration of time. The plurality of MAC units can perform a first plurality of multiplication operations utilizing the first half of the plurality of data values and can perform a second plurality of multiplication operations utilizing the second half of the plurality of data values.

Abstract: A memory device can include a first error correction code (ECC) circuitry, a second ECC circuitry, and a multiplexor (MUX). The first ECC circuitry receive first data from a first bank. The second ECC circuitry can receive second data from a second bank. A MUX can receive the first data from the first ECC circuitry and the second data from the second ECC circuitry. The MUX can provide the first data in a first portion of a duration of time. The MUX can provide the second data in a second portion of the duration of time. A processing unit (PU) can perform a first plurality of multiplication operations utilizing the first data provided by the MUX during the first portion of the duration of time and a second plurality of multiplication operations utilizing the second data provided by the MUX during the second portion of the duration of time.

Abstract: Coupling processing units to data buses in memory is described herein. A data bus coupled to an array of memory cells can receive first data. A processing unit (PU) can be coupled to the data bus. The PU can receive the first data from the data bus. The PU can perform a plurality of operations utilizing the first data to generate second data. The PU can provide the second data to the data bus to store the second data in the array of memory cells.

Abstract: Address offset in memory is described herein. The controller of a memory device can receive an address associated with a bank of memory cells. The controller can access an address offset value that corresponds to the bank of memory cells. The controller can update the address utilizing the address offset value. The controller can provide the updated address to a row decoder. The row decoder can receive the updated address and activate a row of a bank of memory cells utilizing the updated address.

Abstract: The PU of a memory device can receive a matrix of data values and a vector of data values stored in the bank. The PU can perform a first plurality of multiplication operations on a first data value of the vector utilizing a first plurality of data values of a first column of the matrix. The first plurality of multiplication operations can be performed by a plurality of multiply-accumulate (MAC) units. Each of the first plurality of multiplication operations can be performed by a different MAC unit of the plurality of MAC units. The PU can perform a second plurality of multiplication operations on a second data value of the vector utilizing a second plurality of data values of a second column of the matrix. Each of the second plurality of multiplication operations can be performed by a different MAC unit of the plurality of MAC units.

Abstract: A processing unit can include an activation function unit. Data can be received at a plurality of registers of a processing unit of a memory sub-system. The data can be received at a multiply-accumulate (MAC) unit coupled to the plurality of registers. The first plurality of operations can be performed at the MAC unit to generate a first output. The first output can be provided to the activation function unit. The first output can be provided from the AFU to the plurality of registers utilizing a bus or a signal line that couples the plurality of registers to the AFU.

Abstract: Processing can occur in registers of a memory sub-system. A first plurality of registers coupled to the plurality of sense amplifiers can store the first plurality of bits received from the plurality of sense amplifiers. Processing circuitry coupled to the first plurality of registers can receive the first plurality of bits from the first plurality of registers and can perform an operation on the first plurality of bits to generate result bits. A second plurality of registers coupled to the processing circuitry and the plurality of registers can store the result bits received from the processing circuitry and can provide the result bits to a plurality of data input/output (I/O) lines prior to storing a second plurality of bits.

Abstract: Methods and apparatuses related to using non-zero selection circuitry. For example, the non-zero selection circuitry can determine whether a first word received from a first group of sense amplifiers has at least one bit having a first binary value, such as a logical “1”. In response to the first word being determined to have at least one bit having the first binary value, the first word can be outputted from the non-zero selection circuitry and a second word can be prevented from being outputted (even if the second word is determined to have at least one bit having the first binary value) at least while the first word is being outputted.

Abstract: Methods, systems, and devices related to performing logical operations using multiple digit lines. At least two digit lines coupled to the same sense amplifier can be used for the logical operations. For example, two word lines on one digit line and one word line on another digit line can be substantially concurrently activated to perform a particular logical operation. These three word lines are respectively coupled to memory cells configured to store either operands of operation or a reference data value for the particular logical.

Abstract: Methods, systems, and devices related to sense amplifiers of a memory device serving as a Static Random Access Memory (SRAM) cache. For example, a memory array can be coupled to sense amplifiers. In a first mode, the sense amplifiers can be electrically disconnect from digit lines of the memory array. In the first mode, data and metadata of a cache line can be stored in the sense amplifiers when electrically disconnected from the number of digit lines. In the first mode, a portion of the data can be communicated, based on the metadata, from the sense amplifiers to the processing device. In a second mode, the sense amplifiers can connect to the memory array and sense data from the memory array.

Abstract: A touring motorcycle modification kit comprising: an internal frame, an external frame, and a fender; wherein the fender is situated between the internal and external frames; wherein the internal frame is situated inside of the fender; wherein the internal frame comprises two portions, and wherein the two portions are bolted together; wherein the external frame is mounted on the fender at three frame mounting points; wherein two of the three frame mounting points are located on the exterior of the fender; wherein none of the three frame mounting points is located inside of the fender; wherein the external frame does not bolt to the frame mounting points but is releasably attached to the three frame mounting points; and wherein no tools are required to install or remove the external frame. The present invention can be used with a factory seat, exhaust system, wiring harness, saddle bags and tour pack.

Abstract: A touring motorcycle modification kit comprising: an internal frame, an external frame, and a fender; wherein the fender is situated between the internal and external frames; wherein the internal frame is situated inside of the fender; wherein the internal frame comprises two portions, and wherein the two portions are bolted together; wherein the external frame is mounted on the fender at three frame mounting points; wherein two of the three frame mounting points are located on the exterior of the fender; wherein none of the three frame mounting points is located inside of the fender; wherein the external frame does not bolt to the frame mounting points but is releasably attached to the three frame mounting points; and wherein no tools are required to install or remove the external frame. The present invention can be used with a factory seat, exhaust system, wiring harness, saddle bags and tour pack.

Abstract: A laminated photo-emulsioned substrate for use in customizing a wide variety of articles, and a process for making the substrate, is disclosed.

Abstract: A coated product is provided that is comprised of a substrate and a coating comprised of a microporous scaffold material having a high void volume and open, interconnecting void microstructure, the scaffold material having a layer of a selected polyurethane thereon which extends in the voids. The coated product has good barrier properties with respect to bacteria, viruses, and air-borne particulate.

Abstract: Physical exercising apparatus comprising a first part adapted to be mounted generally vertically, a second part having a track and a user support movable horizontally along the track, an assembly adapted to be detachably secured in turn to the first part and to the second part and having a carrier member, preferably having a channel section body, on which is mounted a handle and a device for resisting movement of the handle, whereby so called wall exercises can be performed when the assembly is secured to the first part and so called rowing exercises can be performed when the assembly is secured to the second part. The detachable assembly preferably comprises a lever pivotally mounted on the carrier member, the handle being mounted on the lever. The device for resisting movement of the handle preferably comprises a piston and cylinder device pivotally mounted on the carrier and an adjustable fastener connecting the piston and cylinder device to the lever.

Abstract: A rowing-type exerciser having a retractable seat support portion is collapsible for compact storage.

Abstract: A physical exercising apparatus having at least one force-resistive, movable handle. Two generally perpendicular user supports enable the apparatus to be used in two different positions so as to increase the range of exercises which can be performed.