Abstract: A memory buffer, memory system and method for power-on initialization and test for a cascade interconnect memory system. The memory buffer includes a bus interface to links in a high-speed channel for communicating with a memory controller via a direct connection or via a cascade interconnection through an other memory buffer. The interface is operable in a SBC mode and a high-speed mode. The memory buffer also includes a field service interface (FSI) slave for receiving FSI signals from a FSI master. In addition, the memory buffer includes logic for executing a power-on and initialization training sequence initiated by the memory controller.

Abstract: A memory buffer, memory system and method for power-on initialization and test for a cascade interconnect memory system. The memory buffer includes a bus interface to links in a high-speed channel for communicating with a memory controller via a direct connection or via a cascade interconnection through an other memory buffer. The interface is operable in a SBC mode and a high-speed mode. The memory buffer also includes a field service interface (FSI) slave for receiving FSI signals from a FSI master. In addition, the memory buffer includes logic for executing a power-on and initialization training sequence initiated by the memory controller.

Abstract: A method of passivating etched mirror facets of semiconductor laser diodes which enhances device reliability.The etched mirror facet is first subjected to a weet-etch process to substantially remove any native oxide as well as any surface layer which may have been mechanically damaged during the preceding mirror etch process. Then, a passivation pre-treatment is applied whereby any residual oxygen is removed and a sub-monolayer is formed which permanently reduces the non-radiative recombination of minority carriers at the mirror facet. Finally, the pre-treated mirror surface is coated with a passivation layer to avoid any environmental effect on the mirror.

Abstract: A method, and device produced therewith, for improving the planarity of etched mirror facets 18 of integrated optic structures with non-planar stripe waveguides, such as ridge or groove diode lasers or passive devices such as modulators and switches. The curvature of the mirror facet surface at the edges of the waveguide due to topographical, lithographical and etch process effects, causes detrimental phase distortions, and is avoided by widening the waveguide end near the mirror surface thereby shifting the curved facet regions away from the light mode region to surface regions where curvature is not critical.

Abstract: An integrated semiconductor structure with optically coupled laser diode (11) and photodiode 12A, both devices having etched, vertical facets (16A, 21). The photodiode has a spatially non-uniform sensitivity profile with respect to the incident light beam (18A) emitted by the laser. This is due to the varying distance from the laser facet and/or to variations in the angle of incidence and results in photocurrents produced by the photodiode that depend on the intensity distribution of the light beam. The spatially non-uniform sensitivity profile allows the measurement of the far-field intensity distribution of the laser and thus on-wafer screening of lasers with respect to their mode stability.

Abstract: A method, and device produced therewith, for improving the planarity of etched mirror facets 18 of integrated optic structures with non-planar stripe waveguides, such as ridge or groove diode lasers or passive devices such as modulators and switches. The curvature of the mirror facet surface at the edges of the waveguide due to topographical, lithographical and etch process effects, causes detrimental phase distortions, and is avoided by widening the waveguide end near the mirror surface thereby shifting the curved facet regions away from the light mode region to surface regions where curvature is not critical.

Abstract: A process for forming sidewalls for use in the fabrication of semiconductor structures, where the thin, vertical sidewalls are "image transferred" to define sub-micron lateral dimensions.First, a patterned resist profile with substantially vertical edges is formed on a substrate on which the sidewalls are to be created. Then, the profile is soaked in a reactive organometallic silylation agent to silylate the top and the vertical edges of the resist to a predetermined depth, thereby rendering the profile surfaces highly oxygen etch resistant. In a subsequent anisotropic RIE process, the horizontal surfaces of the silylated profile and the unsilylated resist are removed, leaving the silylated vertical edges, that provide the desired free-standing sidewalls, essentially unaffected.

Abstract: Process for producing temperature-stable undercut profiles for use in semiconductor fabrication. The process is based on the phenomenon of high etch-rate selectivity between RF- and LF- PECVD-grown silicon nitride films (12G and 13G, respectively) that are deposited on top of each other. By choosing proper film and process parameters, these PECVD nitride structures can be made stress-free: the tensile stress of the RF film (12G) compensates the compressive stress of the LF film (13G).Also disclosed is an application of a T-shaped structure (15), produced with the new process, in a method for fabricating fully self-aligned "dummy" gate sub-micron MESFETs.