Patents by Inventor Peter L. Doyle
Peter L. Doyle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11941169Abstract: One embodiment of a virtual reality apparatus comprises: a graphics processing engine comprising a plurality of graphics processing stages, the graphics processing engine to render a plurality of image frames for left and right displays of a head mounted display (HMD); and foveation control hardware logic to independently control two or more of the plurality of graphics processing stages based on feedback received from an eye tracking module of the HMD, the feedback indicating a foveated region selected based on a current or anticipated direction of a user's gaze, the foveation control hardware logic to cause the two or more of the graphics processing stages to process the foveated region differently than other regions of the image frames.Type: GrantFiled: March 1, 2022Date of Patent: March 26, 2024Assignee: Intel CorporationInventors: Ingo Wald, Brent E. Insko, Prasoonkumar Surti, Adam T. Lake, Peter L. Doyle, Daniel Pohl
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Publication number: 20240086138Abstract: In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.Type: ApplicationFiled: September 26, 2023Publication date: March 14, 2024Inventors: Eric J. Asperheim, Subramaniam Maiyuran, Kiran C. Veernapu, Sanjeev S. Jahagirdar, Balaji Vembu, Devan Burke, Philip R. Laws, Kamal Sinha, Abhishek R. Appu, Elmoustapha Ould-Ahmed-Vall, Peter L. Doyle, Joydeep Ray, Travis T. Schluessler, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Altug Koker
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Patent number: 11816384Abstract: In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.Type: GrantFiled: October 4, 2022Date of Patent: November 14, 2023Assignee: Intel CorporationInventors: Eric J. Asperheim, Subramaniam Maiyuran, Kiran C. Veernapu, Sanjeev S. Jahagirdar, Balaji Vembu, Devan Burke, Philip R. Laws, Kamal Sinha, Abhishek R. Appu, Elmoustapha Ould-Ahmed-Vall, Peter L. Doyle, Joydeep Ray, Travis T. Schluessler, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Altug Koker
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Publication number: 20230142472Abstract: In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.Type: ApplicationFiled: October 4, 2022Publication date: May 11, 2023Inventors: Eric J. Asperheim, Subramaniam Maiyuran, Kiran C. Veernapu, Sanjeev S. Jahagirdar, Balaji Vembu, Devan Burke, Philip R. Laws, Kamal Sinha, Abhishek R. Appu, Elmoustapha Ould-Ahmed-Vall, Peter L. Doyle, Joydeep Ray, Travis T. Schluessler, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Altug Koker
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Patent number: 11551400Abstract: A virtual reality apparatus and method are described for tile-based rendering. For example, one embodiment of an apparatus comprises: a set of on-chip geometry buffers including a first buffer to store geometry data, and a set of pointer buffers to store pointers to the geometry data; a tile-based immediate mode rendering (TBIMR) module to perform tile-based immediate mode rendering using geometry data and pointers stored within the set of on-chip geometry buffers; spill circuitry to determine when the on-chip geometry buffers are over-subscribed and responsively spill additional geometry data and/or pointers to an off-chip memory; and a prefetcher to start prefetching the geometry data from the off-chip memory as space becomes available within the on-chip geometry buffers, the TBIMR module to perform tile-based immediate mode rendering using the geometry data prefetched from the off-chip memory.Type: GrantFiled: October 16, 2020Date of Patent: January 10, 2023Assignee: INTEL CORPORATIONInventors: Prasoonkumar Surti, Tomas G. Akenine-Moller, David J. Cowperthwaite, Kun Tian, Peter L. Doyle, Brent E. Insko, Adam T. Lake
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Patent number: 11531510Abstract: In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.Type: GrantFiled: August 11, 2021Date of Patent: December 20, 2022Assignee: Intel CorporationInventors: Eric J. Asperheim, Subramaniam M. Maiyuran, Kiran C. Veernapu, Sanjeev S. Jahagirdar, Balaji Vembu, Devan Burke, Philip R. Laws, Kamal Sinha, Abhishek R. Appu, Elmoustapha Ould-Ahmed-Vall, Peter L. Doyle, Joydeep Ray, Travis T. Schluessler, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Altug Koker
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Patent number: 11514721Abstract: Systems, apparatuses, and methods may provide for technology to dynamically control a display in response to ocular characteristic measurements of at least one eye of a user.Type: GrantFiled: April 2, 2021Date of Patent: November 29, 2022Assignee: Intel CorporationInventors: Radhakrishnan Venkataraman, James M. Holland, Sayan Lahiri, Pattabhiraman K, Kamal Sinha, Chandrasekaran Sakthivel, Daniel Pohl, Vivek Tiwari, Philip R. Laws, Subramaniam Maiyuran, Abhishek R. Appu, ElMoustapha Ould-Ahmed-Vall, Peter L. Doyle, Devan Burke
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Publication number: 20220261075Abstract: One embodiment of a virtual reality apparatus comprises: a graphics processing engine comprising a plurality of graphics processing stages, the graphics processing engine to render a plurality of image frames for left and right displays of a head mounted display (HMD); and foveation control hardware logic to independently control two or more of the plurality of graphics processing stages based on feedback received from an eye tracking module of the HMD, the feedback indicating a foveated region selected based on a current or anticipated direction of a user's gaze, the foveation control hardware logic to cause the two or more of the graphics processing stages to process the foveated region differently than other regions of the image frames.Type: ApplicationFiled: March 1, 2022Publication date: August 18, 2022Inventors: Ingo WALD, Brent E. INSKO, Prasoonkumar SURTI, Adam T. LAKE, Peter L. DOYLE, Daniel POHL
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Patent number: 11398006Abstract: Systems, apparatuses and methods may provide for technology that determines a position associated with one or more polygons in unresolved surface data and select an anti-aliasing sample rate based on a state of the one or more polygons with respect to the position. Additionally, the unresolved surface data may be resolved at the position in accordance with the selected anti-aliasing sample rate, wherein the selected anti-aliasing sample rate varies across a plurality of pixels. The position may be a bounding box, a display screen coordinate, and so forth.Type: GrantFiled: January 11, 2021Date of Patent: July 26, 2022Assignee: Intel CorporationInventors: Abhishek R. Appu, Joydeep Ray, Peter L. Doyle, Subramaniam Maiyuran, Devan Burke, Philip R. Laws, ElMoustapha Ould-Ahmed-Vall, Altug Koker
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Publication number: 20220076479Abstract: Systems, apparatuses and methods may provide for technology that optimizes tiled rendering for workloads in a graphics pipeline including tessellation and use of a geometry shader. More particularly, systems, apparatuses and methods may provide a way to generate, by a write out fixed-function stage, one or more bounding volumes based on geometry data, as inputs to one or more stages of the graphics pipeline. The systems, apparatuses and methods may compute multiple bounding volumes in parallel, and improve the gamer experience, and enable photorealistic renderings at full speed, (e.g., such as human skin and facial expressions) that render three-dimensional (3D) action more realistically.Type: ApplicationFiled: August 12, 2021Publication date: March 10, 2022Applicant: Intel CorporationInventor: Peter L. Doyle
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Patent number: 11269409Abstract: One embodiment of a virtual reality apparatus comprises: a graphics processing engine comprising a plurality of graphics processing stages, the graphics processing engine to render a plurality of image frames for left and right displays of a head mounted display (HMD); and foveation control hardware logic to independently control two or more of the plurality of graphics processing stages based on feedback received from an eye tracking module of the HMD, the feedback indicating a foveated region selected based on a current or anticipated direction of a user's gaze, the foveation control hardware logic to cause the two or more of the graphics processing stages to process the foveated region differently than other regions of the image frames.Type: GrantFiled: May 5, 2020Date of Patent: March 8, 2022Assignee: INTEL CORPORATIONInventors: Ingo Wald, Brent E. Insko, Prasoonkumar Surti, Adam T. Lake, Peter L. Doyle, Daniel Pohl
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Publication number: 20220066726Abstract: In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.Type: ApplicationFiled: August 11, 2021Publication date: March 3, 2022Inventors: Eric J. Asperheim, Subramaniam M. Maiyuran, Kiran C. Veernapu, Sanjeev S. Jahagirdar, Balaji Vembu, Devan Burke, Philip R. Laws, Kamal Sinha, Abhishek R. Appu, Elmoustapha Ould-Ahmed-Vall, Peter L. Doyle, Joydeep Ray, Travis T. Schluessler, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Altug Koker
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Publication number: 20210357618Abstract: Systems, apparatuses, and methods may provide for technology to dynamically control a display in response to ocular characteristic measurements of at least one eye of a user.Type: ApplicationFiled: April 2, 2021Publication date: November 18, 2021Inventors: Radhakrishnan Venkataraman, James M. Holland, Sayan Lahiri, Pattabhiraman K, Kamal Sinha, Chandrasekaran Sakthivel, Daniel Pohl, Vivek Tiwari, Philip R. Laws, Subramaniam Maiyuran, Abhishek R. Appu, ElMoustapha Ould-Ahmed-Vall, Peter L. Doyle, Devan Burke
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Publication number: 20210272230Abstract: Systems, apparatuses and methods may provide for technology that determines a position associated with one or more polygons in unresolved surface data and select an anti-aliasing sample rate based on a state of the one or more polygons with respect to the position. Additionally, the unresolved surface data may be resolved at the position in accordance with the selected anti-aliasing sample rate, wherein the selected anti-aliasing sample rate varies across a plurality of pixels. The position may be a bounding box, a display screen coordinate, and so forth.Type: ApplicationFiled: January 11, 2021Publication date: September 2, 2021Applicant: Intel CorporationInventors: Abhishek R. Appu, Joydeep Ray, Peter L. Doyle, Subramaniam Maiyuran, Devan Burke, Philip R. Laws, ElMoustapha Ould-Ahmed-Vall, Altug Koker
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Patent number: 11099800Abstract: In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.Type: GrantFiled: May 22, 2020Date of Patent: August 24, 2021Assignee: Intel CorporationInventors: Eric J. Asperheim, Subramaniam M. Maiyuran, Kiran C. Veernapu, Sanjeev S. Jahagirdar, Balaji Vembu, Devan Burke, Philip R. Laws, Kamal Sinha, Abhishek R. Appu, Elmoustapha Ould-Ahmed-Vall, Peter L. Doyle, Joydeep Ray, Travis T. Schluessler, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Altug Koker
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Patent number: 11094102Abstract: Systems, apparatuses and methods may provide for technology that optimizes tiled rendering for workloads in a graphics pipeline including tessellation and use of a geometry shader. More particularly, systems, apparatuses and methods may provide a way to generate, by a write out fixed-function stage, one or more bounding volumes based on geometry data, as inputs to one or more stages of the graphics pipeline. The systems, apparatuses and methods may compute multiple bounding volumes in parallel, and improve the gamer experience, and enable photorealistic renderings at full speed, (e.g., such as human skin and facial expressions) that render three-dimensional (3D) action more realistically.Type: GrantFiled: February 21, 2020Date of Patent: August 17, 2021Assignee: Intel CorporationInventor: Peter L. Doyle
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Patent number: 11004265Abstract: Systems, apparatuses and methods may provide a way to subdivide a patch generated in graphics processing pipeline into sub-patches, and generate sub-patch tessellations for the sub-patches. More particularly, systems, apparatuses and methods may provide a way to diverge tessellation sizes to a configurable size within an interior region of a patch or sub-patches based on a position of each of the tessellations. The systems, apparatuses and methods may determine a number of tessellation factors to use based on one or more of a level of granularity of one or more domains of a scene to be digitally rendered, available computing capacity, or power consumption to compute the number of tessellation factors.Type: GrantFiled: February 6, 2019Date of Patent: May 11, 2021Assignee: Intel CorporationInventors: Peter L. Doyle, Devan Burke, Subramaniam Maiyuran, Abhishek R. Appu, Joydeep Ray, Elmoustapha Ould-Ahmed-Vall, Philip R. Laws, Altug Koker
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Patent number: 10970538Abstract: Systems, apparatuses, and methods may provide for technology to dynamically control a display in response to ocular characteristic measurements of at least one eye of a user.Type: GrantFiled: November 6, 2018Date of Patent: April 6, 2021Assignee: Intel CorporationInventors: Radhakrishnan Venkataraman, James M. Holland, Sayan Lahiri, Pattabhiraman K, Kamal Sinha, Chandrasekaran Sakthivel, Daniel Pohl, Vivek Tiwari, Philip R. Laws, Subramaniam Maiyuran, Abhishek R. Appu, Eimoustapha Ould-Ahmed-Vall, Peter L. Doyle, Devan Burke
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Patent number: 10930060Abstract: An embodiment of a conditional shader apparatus may include a conditional pixel shader to determine if one or more pixels meet a shader condition, and a pixel regrouper communicatively coupled to the conditional pixel shader to regroup pixels based on whether the one or more pixels are determined to meet the shader condition. Another embodiment of a conditional shader apparatus may include a thread analyzer to determine if a set of threads meet a thread condition, and a conditional kernel loader communicatively coupled to the thread analyzer to load an appropriate kernel from a set of two or more kernels based on whether the set of threads are determined to meet the thread condition. Other embodiments are disclosed and claimed.Type: GrantFiled: February 6, 2019Date of Patent: February 23, 2021Assignee: Intel CorporationInventors: Prasoonkumar Surti, Karthik Vaidyanathan, Murali Ramadoss, Michael Apodaca, Abhishek Venkatesh, Devan Burke, Philip R. Laws, Subramaniam Maiyuran, Abhishek R. Appu, Elmoustapha Ould-Ahmed-Vall, Peter L. Doyle
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Publication number: 20210035348Abstract: A virtual reality apparatus and method are described for tile-based rendering. For example, one embodiment of an apparatus comprises: a set of on-chip geometry buffers including a first buffer to store geometry data, and a set of pointer buffers to store pointers to the geometry data; a tile-based immediate mode rendering (TBIMR) module to perform tile-based immediate mode rendering using geometry data and pointers stored within the set of on-chip geometry buffers; spill circuitry to determine when the on-chip geometry buffers are over-subscribed and responsively spill additional geometry data and/or pointers to an off-chip memory; and a prefetcher to start prefetching the geometry data from the off-chip memory as space becomes available within the on-chip geometry buffers, the TBIMR module to perform tile-based immediate mode rendering using the geometry data prefetched from the off-chip memory.Type: ApplicationFiled: October 16, 2020Publication date: February 4, 2021Inventors: Prasoonkumar SURTI, Tomas G. AKENINE-MOLLER, David J. COWPERTHWAITE, Kun TIAN, Peter L. DOYLE, Brent E. INSKO, Adam T. LAKE