Patents by Inventor Peter L. Doyle

Peter L. Doyle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030123089
    Abstract: Embodiments of the present invention provide a mechanism to track and manage graphics states, in particular slow state variables, for use with a tile-based rendering architecture such as zone rendering. Slow state variables, including but not limited to infrequently changing state variables, large state variables (e.g., matrices) and state variables which require rendering pipeline flushes (e.g., texture palette changes), are maintained in a global (i.e., scene-scoped) list of slow state blocks. Since the driver software only needs to maintain a single list of slow state blocks for the entire scene, replication of slow state variables into bins is avoided.
    Type: Application
    Filed: December 31, 2001
    Publication date: July 3, 2003
    Inventor: Peter L. Doyle
  • Publication number: 20030122836
    Abstract: The present invention optimizes graphics performance during zone rendering by providing an automatic management of bin memory between the binning and rendering phases. Embodiments of the present invention provide a mechanism by which the binner and renderer automatically share a pool of physical memory pages in order to build bin buffers and recycle them after they have been used in rendering. This is performed in such a fashion that multiple binned scenes can be queued up concurrently, with no requirement for software intervention except under exceptional conditions. The need for software management of zone rendering bin buffer memory is thus eliminated. Multiple scenes for binning and rendering can also be queued without software intervention.
    Type: Application
    Filed: December 31, 2001
    Publication date: July 3, 2003
    Inventors: Peter L. Doyle, Aditya Sreenivas
  • Publication number: 20030122835
    Abstract: A depth write disable apparatus and method for controlling evictions, such as depth values, from a depth cache to a corresponding depth buffer in a zone rendering system. When the depth write disable circuitry is enabled, evictions from the depth cache (as which typically occur during the rendering of the next zone) to the depth buffer are prevented. In particular, once the depth buffer is initialized (i.e. cleared) to a constant value at the beginning of a scene, the depth buffer does not need to be read. The depth cache handles intermediate depth reads and writes within each zone. Since the memory resident depth buffer is not required after a scene is rendered, it never needs to be written. The final depth values for a zone can thus be discarded (i.e., rather than written to the depth buffer) after each zone is rendering.
    Type: Application
    Filed: December 31, 2001
    Publication date: July 3, 2003
    Inventors: Peter L. Doyle, Aditya Sreenivas
  • Publication number: 20030063087
    Abstract: A method is provided for performing a depth test for an image in a graphics system. This may include determining a format of a depth buffer device and storing a value associated with a pixel of the image in the depth buffer device based on the determined format of the depth buffer device. In the depth test, a value associated with a current pixel may be compared to the value stored in the depth buffer device in the determined format.
    Type: Application
    Filed: September 28, 2001
    Publication date: April 3, 2003
    Inventors: Peter L. Doyle, William B. Sadler
  • Publication number: 20030001847
    Abstract: A method, apparatus, and system to concurrently render independent images for display on one or more display devices. In an embodiment, a graphics-rendering engine concurrently renders independent images for display on multiple display devices. A time allocator arbitrates the concurrent use of the graphics-rendering engine between each independent image being rendered.
    Type: Application
    Filed: June 29, 2001
    Publication date: January 2, 2003
    Inventors: Peter L. Doyle, Aditya Sreenivas
  • Publication number: 20030001857
    Abstract: A computer system and method are provided for mapping of texture images. This may include a memory device to store a plurality of texture coordinates associated with vertices of three dimensional objects and a graphics device coupled to the memory device to process internal texture coordinates. A mapping system may appropriately route select ones of the plurality of texture coordinates from the memory device to the graphics device. The texture images may be mapped onto objects that, when rendered, include the image that may later be displayed on a display device.
    Type: Application
    Filed: June 29, 2001
    Publication date: January 2, 2003
    Inventor: Peter L. Doyle
  • Publication number: 20030001848
    Abstract: A method, apparatus, and system to concurrently render independent images for display on one or more display devices. In an embodiment, a graphics-rendering engine concurrently renders independent images for display on multiple display devices. A graphics context manager stores in a first memory area and restores from the first memory area information describing a first rendering context associated with a first independent image. The graphics context manager stores in a second memory area and restores from the second memory area information describing a second rendering context associated with a second independent image.
    Type: Application
    Filed: June 29, 2001
    Publication date: January 2, 2003
    Inventors: Peter L. Doyle, Aditya Sreenivas
  • Patent number: 6429873
    Abstract: A method and circuit for determining the address of texture maps in memory, when only the base address of the primary texture map is known. The various maps associated with a given texture are sized and stored in a manner that allows any texel in any of the maps to be located based on the map number and the base address of the primary map. A circuit is provided that determines the necessary addresses with minimal calculations.
    Type: Grant
    Filed: December 29, 1999
    Date of Patent: August 6, 2002
    Assignee: Intel Corporation
    Inventors: Nicolas I. Kacevas, Val G. Cook, Peter L. Doyle
  • Patent number: 5251322
    Abstract: A method and apparatus for operating a computer graphics system to perform a conditional test on a node in a graphics data structure during the traversal of the graphics data structure by a structure walker. The graphics system is operated to manipulate data contained in a memory to define a value for an operand that is to be tested. The system accesses the operand from the memory. A structure walker performs a test on the value of the operand during traversal of the graphics data structure. Depending upon the result of the test, the structure walker traverses one of several paths in the graphics data structure to create a graphics display.
    Type: Grant
    Filed: February 8, 1990
    Date of Patent: October 5, 1993
    Assignee: Digital Equipment Corporation
    Inventors: Peter L. Doyle, John P. Ellenberger, Ellis O. Jones, David C. Carver, Steven D. DiPirro, Branko J. Gerovac, William P. Armstrong, Ellen S. Gibson, Raymond E. Shapiro, Kevin C. Rushforth, William C. Roach
  • Patent number: 5155822
    Abstract: A stand-alone graphics workstation including a digital computer host and a graphics processing subsystem is disclosed. Address data relating to the graphics subsystem components is mapped into the host system virtual memory. The application processes residing in the host are thereby able to communicate directly with the graphics subsystem components, as, e.g. the structure memory, without the need of a direct memory access hardware arrangement or device drivers.
    Type: Grant
    Filed: August 13, 1987
    Date of Patent: October 13, 1992
    Assignee: Digital Equipment Corporation
    Inventors: Peter L. Doyle, John P. Ellenberger, Ellis O. Jones, David C. Carver, Steven D. DiPirro, Branko J. Gerovac, William P. Armstrong, Ellen S. Gibson, Raymond E. Shapiro, Kevin C. Rutherford, William C. Roach
  • Patent number: 5097411
    Abstract: A method for operating a computer graphics system to build custom nodes containing commands and data information that is stored in a data structure in the graphics subsystem. A host processor calls routines which build the custome nodes. A structure walker traverses the data structure and extracts the information from the data structure to pass it to the graphics subsystem for display. The use of custom nodes increases the flexibility of advanced graphics data structures bny allowing the creation of other data structures during execution of a first data structure.
    Type: Grant
    Filed: October 17, 1988
    Date of Patent: March 17, 1992
    Assignee: Digital Equipment Corporation
    Inventors: Peter L. Doyle, John P. Ellenberger, Ellis O. Jones, David C. Carver, Steven D. Dipirro, Branko J. Gerovac, William P. Armstrong, Ellen S. Gibson, Raymond E. Shapiro, Kevin C. Rushforth, William C. Roach
  • Patent number: 4928247
    Abstract: A host system executes one or more application programs which results in graphic data structures. These graphic data structures are then continuously and asynchronously traversed. Traversal requests by competing application programs are scheduled and performed so that each application views the graphics processing as its own. The traversal and ordering of traversal requests provide efficient use of resources for multiple application programs.
    Type: Grant
    Filed: April 20, 1988
    Date of Patent: May 22, 1990
    Assignee: Digital Equipment Corporation
    Inventors: Peter L. Doyle, John P. Ellenberger, Ellis O. Jones, David C. Carver, Steven D. DiPirro, Branko J. Gerovac, William P. Armstrong, Ellen S. Gibson, Raymond E. Shapiro, Kevin C. Rushforth, William C. Roach