Abstract: A method and apparatus for generating a serial test pattern for sequence detection. The serial test pattern has a first plurality of bits and is generated by a pattern generator. A second plurality of bits is generated having a first value. The second plurality of bits includes less bits than the first plurality of bits. The first value of the second plurality of bits is then compared with one or more numbers to generate a comparison result. A next bit is then generated in the serial pattern based upon the comparison result and one or more bits of the second plurality of bits.

Abstract: A device 11 includes a sync unit 20 to identify and achieve synchronization with the cell boundaries of a 53-byte ATM cell stream. Each cell starts with a 5-byte header in which the 5th byte is a CRC byte. Instead of testing all possible bytes to see whether they are cell boundaries, a CRC circuit 21 computes CRCs for successive 5-byte blocks, under the control of a 5-state header counter 22. If such a block is a header, its CRC is a predetermined value, and a match signal is sent to a logic circuit 23, which starts a 53-state cell counter 24 and stops the header counter 22. A 4-state repeat counter 25 checks that the next 5 blocks checked by the CRC circuit 21 are also headers, as confirmation. Synchronization is achieved within at most 5 cells, because the test period of the testing circuitry (which could be longer than the header length) is coprime with the cell length.