Abstract: A line driver which is especially suitable for wirebound data transmission at high bit rates, comprising several parallel-connected driver stages (3) respectively comprising a first pair of transistors consisting of two transistors (4, 5) which are controlled in a differential manner according to digital data to be transmitted, and a second pair of transistors (4, 5). The transistors belonging to the second pair of transistors (6, 7) are series-connected to a corresponding transistor (4, 5) of the first pair of transistors. The individual driver stages (3) are connected by the transistors (6, 7) of the second pair of transistors in a parallel manner to both the terminals of the line driver. Each driver stage (3) is associated with a control circuit (2) with transfer gates (14, 15), producing the differential control signals (VGA, VGB) for the two transistors (4, 5) of the corresponding first pair of transistors.

Abstract: A crest factor reduction circuit for reducing a crest factor (CF) of a multi-tone-data signal which is transmitted in a predetermined transmission frequency band, wherein the crest factor reduction circuit (8) comprises means (34) for subtracting a multi-tone-correction signal from said multi-tone-data signal, wherein the multi-tone-correction signal comprises a plurality of tone signals having frequencies outside said transmission frequency band.

Abstract: A line driver (3) for transmitting data with high bit rates, in particular for wire-bound data transmission in the full-duplex process, comprises a differential pair with differential pair transistors (14, 15) for generating transmission impulses as a function of the data to be transmitted, whereby the transmission impulses are preferably output via cascode transistors (16, 17), each with the differential pair transistors (14, 15) forming a cascode circuit, onto the data transmission line (8, 9) connected to the line driver (3).

Abstract: A line driver which is especially suitable for wirebound data transmission at high bit rates, comprising several parallel-connected driver stages (3) respectively comprising a first pair of transistors consisting of two transistors (4, 5) which are controlled in a differential manner according to digital data to be transmitted, and a second pair of transistors (4, 5). The transistors belonging to the second pair of transistors (6, 7) are series-connected to a corresponding transistor (4, 5) of the first pair of transistors. The individual driver stages (3) are connected by the transistors (6, 7) of the second pair of transistors in a parallel manner to both the terminals of the line driver. Each driver stage (3) is associated with a control circuit (2) with transfer gates (14, 15), producing the differential control signals (VGA, VGB) for the two transistors (4, 5) of the corresponding first pair of transistors.

Abstract: A circuit arrangement for the analogue suppression of echoes, as in particular can be used in a hybrid-circuit for DSL-transmission systems, comprises a replica (8) for emulating the behaviour of the transmission line (17). In addition, a circuit (3, 4) for emulating the behaviour of the transmitter (13) is provided, which comprises at least one lowpass (3, 4). Furthermore, a replica (9, 10) for emulating the behaviour of bridge taps (14) can also be provided, which comprises at least one bandpass (9, 10). Additionally, a replica (19) for emulating the behaviour of the line driver (1) can also be provided.

Abstract: Sigma-delta A/D converter having at least one analog signal input (1, 2) for applying an analog input signal, a subtraction element (3) having a plurality of capacitors (20) for sampling the input signal during a sampling phase, it being possible during an integration phase to switch the capacitors (20) to reference voltage sources (7, 8, 9) depending on control signals, an integrator (10) for integrating the output signal of the subtraction element (3) during the integration phase, a quantizer (13) for analog-to-digital conversion of the output signal of the integrator (10) for outputting a digitized output signal to a digital signal output (14), and having a control logic element (16) for generating the control signals in such a way that the current load of the reference voltage sources (7, 8, 9) is minimized during the integration phase.

Abstract: Sigma-delta A/D converter having at least one analog signal input (1, 2) for applying an analog input signal, a subtraction element (3) having a plurality of capacitors (20) for sampling the input signal during a sampling phase, it being possible during an integration phase to switch the capacitors (20) to reference voltage sources (7, 8, 9) depending on control signals, an integrator (10) for integrating the output signal of the subtraction element (3) during the integration phase, a quantizer (13) for analog-to-digital conversion of the output signal of the integrator (10) for outputting a digitized output signal to a digital signal output (14), and having a control logic element (16) for generating the control signals in such a way that the current load of the reference voltage sources (7, 8, 9) is minimized during the integration phase.

Abstract: An amplifier output stage is described containing a preliminary stage, a final stage and a control device. The quiescent current that flows through transistors of the final stage is adjusted by the preliminary stage. For this, a current that is proportional to the quiescent current is generated in the control device from which control voltages are derived and controlled. The preliminary stage contains adjustable current sources for adjusting the quiescent current in a final step which are controlled by the control voltages.

Abstract: An amplifier output stage is described containing a preliminary stage, a final stage and a control device. The quiescent current that flows through transistors of the final stage is adjusted by the preliminary stage. For this, a current that is proportional to the quiescent current is generated in the control device from which control voltages are derived and controlled. The preliminary stage contains adjustable current sources for adjusting the quiescent current in a final step which are controlled by the control voltages.