Patents by Inventor Peter Lachner

Peter Lachner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210089427
    Abstract: In one embodiment, an apparatus includes: a first trace source to generate a plurality of first trace messages and a first local platform description identifier to identify the first trace source; a second trace source to generate a plurality of second trace messages and a second local platform description identifier to identify the second trace source; and a trace aggregator coupled to the first and the second trace sources, the trace aggregator to generate a global platform description identifier for the apparatus and output a trace stream including the global platform destination identifier, the first and second local platform description identifiers, the plurality of first trace messages and the plurality of second trace messages. Other embodiments are described and claimed.
    Type: Application
    Filed: December 9, 2020
    Publication date: March 25, 2021
    Inventors: Rolf Kuehnis, Peter Lachner
  • Patent number: 10901871
    Abstract: In one embodiment, an apparatus includes: a first trace source to generate a plurality of first trace messages and a first local platform description identifier to identify the first trace source; a second trace source to generate a plurality of second trace messages and a second local platform description identifier to identify the second trace source; and a trace aggregator coupled to the first and the second trace sources, the trace aggregator to generate a global platform description identifier for the apparatus and output a trace stream including the global platform destination identifier, the first and second local platform description identifiers, the plurality of first trace messages and the plurality of second trace messages. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: January 26, 2021
    Assignee: Intel Corporation
    Inventors: Rolf Kuehnis, Peter Lachner
  • Patent number: 10846439
    Abstract: A system to evaluate functional safety in an integrated circuit. The system includes a first circuit to execute an operation to cause to system to perform a function, where the function associated with a specified safety integrity level. The system also includes second circuit to capture trace data at an interface to the first circuit or at internal signals without inhibiting performance of the function, where the trace data comprising information that is used to determine whether the system can perform the function with an indicated level of functional safety and transmit the trace data to a safety evaluation circuit.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Riccardo Locatelli, Peter Lachner, Riccardo Mariani, Michael Paulitsch, Kevin Safford
  • Publication number: 20200285559
    Abstract: In one embodiment, an apparatus includes: a first hardware circuit to execute operations and a trace hardware circuit coupled to the first hardware circuit. At least one virtualization environment to be instantiated by a virtualization environment controller is to execute on the first hardware circuit. The virtualization environment controller may receive from a first virtualization environment a first trace message and a first platform description identifier to identify the first virtualization environment, remap the first platform description identifier to a second platform description identifier and send the first trace message and the second platform description identifier to the trace hardware circuit. In turn, the trace hardware circuit may send the first trace message and the second platform description identifier to a debug and test system. Other embodiments are described and claimed.
    Type: Application
    Filed: May 20, 2020
    Publication date: September 10, 2020
    Inventors: ROLF KUEHNIS, PETER LACHNER
  • Patent number: 10747259
    Abstract: Herein is disclosed a multichip reference logging system comprising a control circuit, configured to generate a reference signal; a first chip, configured to generate a first operations log, the first chip further comprising a first reference circuit, configured to receive the reference signal and to create a first reference event in response to the received reference signal; a memory associated with the first chip, configured to store the first reference event within the first operations log; a second chip, configured to generate a second operations log, the second chip further comprising a second reference circuit, configured to receive the reference signal and to create a second reference event in response to the received reference signal; and a memory associated with the second chip, configured to store the second reference event within the second operations log.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: August 18, 2020
    Assignee: Intel IP Corporation
    Inventors: Uwe Schumacher, Peter Lachner, Andrej Tkalcec, Donald Korinke
  • Publication number: 20190370503
    Abstract: A system to evaluate functional safety in an integrated circuit. The system includes a first circuit to execute an operation to cause to system to perform a function, where the function associated with a specified safety integrity level. The system also includes second circuit to capture trace data at an interface to the first circuit or at internal signals without inhibiting performance of the function, where the trace data comprising information that is used to determine whether the system can perform the function with an indicated level of functional safety and transmit the trace data to a safety evaluation circuit.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 5, 2019
    Inventors: Riccardo Locatelli, Peter Lachner, Riccardo Mariani, Michael Paulitsch, Kevin Safford
  • Publication number: 20190196931
    Abstract: In one embodiment, an apparatus includes: a first trace source to generate a plurality of first trace messages and a first local platform description identifier to identify the first trace source; a second trace source to generate a plurality of second trace messages and a second local platform description identifier to identify the second trace source; and a trace aggregator coupled to the first and the second trace sources, the trace aggregator to generate a global platform description identifier for the apparatus and output a trace stream including the global platform destination identifier, the first and second local platform description identifiers, the plurality of first trace messages and the plurality of second trace messages. Other embodiments are described and claimed.
    Type: Application
    Filed: March 5, 2019
    Publication date: June 27, 2019
    Inventors: Rolf Kuehnis, Peter Lachner
  • Patent number: 10331452
    Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for tracking the mode of processing devices in an instruction tracing system. The method may include receiving an indication of a change in a current execution mode of the processing device. The method may also include determining that the current execution mode of the received indication is different than a value of an execution mode of a first execution mode (EM) packet previously-generated by the IT module. The method may also include generating, based on the determining that the current execution mode is different, a second EM packet that provides a value of the current execution mode of the processing device to indicate the change in the execution mode for an instruction in a trace generated by the IT module. The method may further include generating transactional memory (TMX) packets having n bit mode pattern in the packet log. The n is at least two and the n bit mode indicates transaction status of the TMX operation.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: June 25, 2019
    Assignee: Intel Corporation
    Inventors: Thilo Schmitt, Peter Lachner, Beeman Strong, Ofer Levy, Thomas Toll, Matthew Merten, Tong Li, Ravi Rajwar, Konrad Lai
  • Publication number: 20190050021
    Abstract: Herein is disclosed a multichip reference logging system comprising a control circuit, configured to generate a reference signal; a first chip, configured to generate a first operations log, the first chip further comprising a first reference circuit, configured to receive the reference signal and to create a first reference event in response to the received reference signal; a memory associated with the first chip, configured to store the first reference event within the first operations log; a second chip, configured to generate a second operations log, the second chip further comprising a second reference circuit, configured to receive the reference signal and to create a second reference event in response to the received reference signal; and a memory associated with the second chip, configured to store the second reference event within the second operations log.
    Type: Application
    Filed: December 29, 2017
    Publication date: February 14, 2019
    Inventors: Uwe SCHUMACHER, Peter LACHNER, Andrej TKALCEC, Donald KORINKE
  • Patent number: 10175990
    Abstract: According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: January 8, 2019
    Assignee: Intel Corporation
    Inventors: Christopher J. Hughes, Yen-Kuang (Y. K.) Chen, Mayank Bomb, Jason W. Brandt, Mark J. Buxton, Mark J. Charney, Srinivas Chennupaty, Jesus Corbal, Martin G. Dixon, Milind B. Girkar, Jonathan C. Hall, Hideki (Saito) Ido, Peter Lachner, Gilbert Neiger, Chris J. Newburn, Rajesh S. Parthasarathy, Bret L. Toll, Robert Valentine, Jeffrey G. Wiedemeier
  • Patent number: 10114651
    Abstract: According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: October 30, 2018
    Assignee: Intel Corporation
    Inventors: Christopher J. Hughes, Yen-Kuang (Y. K.) Chen, Mayank Bomb, Jason W. Brandt, Mark J. Buxton, Mark J. Charney, Srinivas Chennupaty, Jesus Corbal, Martin G. Dixon, Milind B. Girkar, Jonathan C. Hall, Hideki (Saito) Ido, Peter Lachner, Gilbert Neiger, Chris J. Newburn, Rajesh S. Parthasarathy, Bret L. Toll, Robert Valentine, Jeffrey G. Wiedemeier
  • Patent number: 10073719
    Abstract: In one embodiment, a processor includes an execution unit and at least one last branch record (LBR) register to store address information of a branch taken during program execution. This register may further store a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction. This register may further store an abort indicator to indicate whether the branch was caused by a transaction abort. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Ravi Rajwar, Peter Lachner, Laura A. Knauth, Konrad K. Lai
  • Publication number: 20180150301
    Abstract: According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.
    Type: Application
    Filed: May 20, 2013
    Publication date: May 31, 2018
    Inventors: Christopher J. Hughes, Yen-Kuang (Y.K.) Chen, Mayank Bomb, Jason W. Brandt, Mark J. Buxton, Mark J. Charney, Srinivas Chennupaty, Jesus Corbal, Martin G. Dixon, Milind B. Girkar, Jonathan C. Hall, Hideki (Saito) Ido, Peter Lachner, Gilbert Neiger, Chris J. Newburn, Rajesh S. Parthasarathy, Bret L. Toll, Robert Valentine, Jeffrey G. Wiedemeier
  • Publication number: 20180129506
    Abstract: According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.
    Type: Application
    Filed: January 4, 2018
    Publication date: May 10, 2018
    Inventors: Christopher J. Hughes, Yen-Kuang (Y.K.) Chen, Mayank Bomb, Jason W. Brandt, Mark J. Buxton, Mark J. Charney, Srinivas Chennupaty, Jesus Corbal, Martin G. Dixon, Milind B. Girkar, Jonathan C. Hall, Hideki (Saito) Ido, Peter Lachner, Gilbert Neiger, Chris J. Newburn, Rajesh S. Parthasarathy, Bret L. Toll, Robert Valentine, Jeffrey G. Wiedemeier
  • Patent number: 9632907
    Abstract: A processing device implementing tracking of deferred data packets in a debug trace architecture is disclosed. The processing device is to determine an order number corresponding to an order in which an instruction was executed relative to other executed instructions that correspond to an instruction type within a sequence of executed instructions, identify a first data packet corresponding to a first packet type and sequentially ordered, according to the order number, with respect to data packets of the first packet type within a data trace log, identify a second data packet corresponding to a second packet type and sequentially ordered, according to the order number, with respect to data packets of the second packet type within the data trace log, and map the identified first and second data packets to the instruction, wherein at least one of the first or second data packets was generated post-retirement of the instruction.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: April 25, 2017
    Assignee: Intel Corporation
    Inventors: Beeman C. Strong, Stephen J. Robinson, Jason W. Brandt, Peter Lachner
  • Patent number: 9612938
    Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for providing status of a processing device with a periodic synchronization point in an instruction tracing system. For example, the method may include generating a boundary packet based on a unique byte pattern in a packet log. The boundary packet provides a starting point for packet decode. The method may also include generating a plurality of state packets based on status information of the processor. The plurality of state packets follows the boundary packet when outputted into the packet log.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: April 4, 2017
    Assignee: Intel Corporation
    Inventors: Frank Binns, Matthew C. Merten, Mayank Bomb, Beeman C. Strong, Peter Lachner, Jason W. Brandt, Itamar Kazachinsky, Ofer Levy, Md A. Rahman
  • Publication number: 20160378636
    Abstract: In an embodiment, a processor includes a core that is to include fetch logic to fetch instructions that include first instructions and a second instruction. The core also includes execution logic to execute the instructions. The execution logic is to retrieve an operand value that is one of an immediate value, a register value, and a memory value stored in a memory location, responsive to execution of the second instruction. The core also includes logic to output a packet that includes a representation of the operand value responsive to execution of the second instruction. The core also includes processor trace (PT) logic to generate a processor trace that includes a plurality of PT packets, where each PT packet correspond to an outcome of execution of a respective first instruction. The processor trace logic is further to include the packet within the processor trace. Other embodiments are described and claimed.
    Type: Application
    Filed: June 26, 2015
    Publication date: December 29, 2016
    Inventors: Beeman C. Strong, Jason W. Brandt, Peter Lachner, Andreas Kleen, James B. Crossland, Toby Opferman
  • Publication number: 20160232041
    Abstract: In one embodiment, a processor includes an execution unit and at least one last branch record (LBR) register to store address information of a branch taken during program execution. This register may further store a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction. This register may further store an abort indicator to indicate whether the branch was caused by a transaction abort. Other embodiments are described and claimed.
    Type: Application
    Filed: April 18, 2016
    Publication date: August 11, 2016
    Inventors: Ravi Rajwar, Peter Lachner, Laura A. Knauth, Konrad K. Lai
  • Publication number: 20160170820
    Abstract: A processing device implementing tracking of deferred data packets in a debug trace architecture is disclosed. The processing device is to determine an order number corresponding to an order in which an instruction was executed relative to other executed instructions that correspond to an instruction type within a sequence of executed instructions, identify a first data packet corresponding to a first packet type and sequentially ordered, according to the order number, with respect to data packets of the first packet type within a data trace log, identify a second data packet corresponding to a second packet type and sequentially ordered, according to the order number, with respect to data packets of the second packet type within the data trace log, and map the identified first and second data packets to the instruction, wherein at least one of the first or second data packets was generated post-retirement of the instruction.
    Type: Application
    Filed: December 10, 2014
    Publication date: June 16, 2016
    Inventors: BEEMAN C. STRONG, STEPHEN J. ROBINSON, JASON W. BRANDT, PETER LACHNER
  • Patent number: 9354878
    Abstract: In one embodiment, a processor includes an execution unit and at least one last branch record (LBR) register to store address information of a branch taken during program execution. This register may further store a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction. This register may further store an abort indicator to indicate whether the branch was caused by a transaction abort. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: May 31, 2016
    Assignee: Intel Corporation
    Inventors: Ravi Rajwar, Peter Lachner, Laura A. Knauth, Konrad K. Lai